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[PATCH, VAX] Correct ffs instruction constraint

VAX' FFS as variable-length bit field instruction uses a "base"
operand of type "vb" meaning "byte address".
"base" can be 32 bits (SI) and due to the definition of
ffssi2/__builtin_ffs() with the operand constraint "m", code can be
emitted which incorrectly implies a mode-dependent (= longword, for
the 32-bit operand) address.
File scsipi_base.c compiled with -Os for our VAX install kernel shows:

    ffs $0x0,$0x20,0x50(r11)[r0],r9

Apparently, 0x50(r11)[r0] as a longword address is assumed to be
evaluated in longword context by FFS, but the instruction expects a
byte address.

Our fix is to change the operand constraint from "m" to "Q", i. e.
"operand is a MEM that does not have a mode-dependent address", which
results in:

    moval 0x50(r11)[r0],r1
    ffs $0x0,$0x20,(r1),r9

MOVAL evaluates the source operand/address in longword context, so
effectively converts the word address to a byte address for FFS.

See NetBSD PR port-vax/51761 ( and
discussion on port-vax mailing list


2017-06-20  Maya Rashish  <>

	* gcc/config/vax/ Correct ffssi2_internal
	instruction constraint.

 gcc/config/vax/ | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/gcc/config/vax/ b/gcc/config/vax/
index fb0f69acb..b78fb5616 100644
--- a/gcc/config/vax/
+++ b/gcc/config/vax/
@@ -41,7 +41,7 @@
 (define_insn "ffssi2_internal"
   [(set (match_operand:SI 0 "nonimmediate_operand" "=rQ")
-	(ffs:SI (match_operand:SI 1 "general_operand" "nrmT")))
+	(ffs:SI (match_operand:SI 1 "general_operand" "nrQT")))
    (set (cc0) (match_dup 0))]
   "ffs $0,$32,%1,%0")

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