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Re: [PATCH v2, rs6000] gcc mainline, add builtin support for vec_float, vec_float2, vec_floate, vec_floate, builtins


On Mon, Jun 12, 2017 at 11:40:17AM -0700, Carl E. Love wrote:
> Michael:
> 
> OK, so sounds like I should stick to the general wa register constraint.
> The third field of the define_expand I have what I believe is called the
> "condition string" as "TARGET_VSX".  Is that the appropriate condition
> string?  I see conditions string "VECTOR_UNIT_VSX_P (V4SFmode)" also
> used.  Segher is thinking that this string would have the same effect as
> "TARGET_VSX"??  How does one select the correct condition string based
> on the register constraint?

In general, the idea was to allow you to turn off VSX support for one type, so
we used VECTOR_UNIT_VSX_P (mode) or VECTOR_MEM_VSX_P (mode) to say where there
were VSX arithmetic operations or memory operations on the particular type.

Note, it becomes an issue for V2DImode, as VECTOR_UNIT_VSX_P (V2DImode) is not
enabled until ISA 2.07 (power8), since we didn't have vector arithmetic
operations on V2DImode until then.

> 
> Here is what I currently have for my define_expand. Is it correct?
> 
> ;; Generate
> float2                                                              
> ;; convert two long long signed ints to float                                   
> (define_expand "float2_v2di"                                                    
>   [(match_operand:V4SF 0 "register_operand" "=wa")                              
>    (unspec:V4SI [(match_operand:V2DI 1 "register_operand" "wa")                 
>                  (match_operand:V2DI 2 "register_operand" "wa")]                
>   UNSPEC_VSX_FLOAT2)]                                                           
>                                                                                 
>   "TARGET_VSX"                                                                  
> {                                                                               
>   rtx rtx_src1, rtx_src2, rtx_dst;                                              
>                                                                                 
>   rtx_dst = operands[0];                                                        
>   rtx_src1 = operands[1];                                                       
>   rtx_src2 = operands[2];                                                       
>                                                                                 
>   rs6000_generate_float2_code (true, rtx_dst, rtx_src1, rtx_src2);              
>   DONE;                                                                         
> })
> 
> Thanks for your help on this.
> 

You can simplify this to:

(define_expand "float2_v2di"                                                    
  [(use (match_operand:V4SF 0 "register_operand"))
   (use (match_operand:V2DI 1 "register_operand"))
   (use (match_operand:V2DI 2 "register_operand"))]
  "TARGET_VSX"                                                                  
{                                                                               
  rtx rtx_src1, rtx_src2, rtx_dst;                                              
                                                                                
  rtx_dst = operands[0];                                                        
  rtx_src1 = operands[1];                                                       
  rtx_src2 = operands[2];                                                       
                                                                                
  rs6000_generate_float2_code (true, rtx_dst, rtx_src1, rtx_src2);              
  DONE;                                                                         
})

Since the gen* pattern never generates the code due to the DONE (the call to
rs6000_generate_float2_code does that).  And since it is a define_expand,
the constraints are not used.

Now, if it had been a define_insn_and_split, then you would have needed the
unspec and the constraints.

-- 
Michael Meissner, IBM
IBM, M/S 2506R, 550 King Street, Littleton, MA 01460-6245, USA
email: meissner@linux.vnet.ibm.com, phone: +1 (978) 899-4797


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