This is the mail archive of the gcc-patches@gcc.gnu.org mailing list for the GCC project.
Index Nav: | [Date Index] [Subject Index] [Author Index] [Thread Index] | |
---|---|---|
Message Nav: | [Date Prev] [Date Next] | [Thread Prev] [Thread Next] |
Other format: | [Raw text] |
Hello! Attached patch allows direct XMM->GR zero extensions for 32bit targets. This insn will be split after reload to a direct XMM->lowpart(GR) move and 0->highpart(GR) zeroing. 2017-05-31 Uros Bizjak <ubizjak@gmail.com> * config/i386/i386.md (*zero_extendsidi2): Enable alternative (?r, *Yj) also for 32bit target. Update insn attributes. (zero-extendsidi2 splitter): Allow all registers for operand 1. Bootstrapped and regression tested on x86_64-linux-gnu {,-m32}. Committed to mainline SVN. Uros.
Attachment:
p.diff.txt
Description: Text document
Index Nav: | [Date Index] [Subject Index] [Author Index] [Thread Index] | |
---|---|---|
Message Nav: | [Date Prev] [Date Next] | [Thread Prev] [Thread Next] |