Re: [PATCH, GCC/ARM, stage4] Set mode for success result of atomic compare and swap

[Kyrill Tkachov <kyrylo dot tkachov at foss dot arm dot com>]

Hi Thomas,

On 12/04/17 09:59, Thomas Preudhomme wrote:
> Hi,
>
> Currently atomic_compare_and_swap<mode>_1 define_insn do not have a mode
> set for the destination of the set indicating the success result of the
> instruction. This is because the operand can be either a CC_Z register
> (for 32-bit targets) or a SI register (for 16-bit Thumb targets). This
> result in lack of checking for the mode.
>
> This commit use a new CCSI iterator to solve this issue while avoiding
> duplication of the patterns. The insn name are kept unique by using
> attributes tied to the iterator (SIDI:mode and CCSI:arch) instead of
> usign the builtin mode attribute. Expander arm_expand_compare_and_swap
> is also adapted accordingly.
>
> ChangeLog entry is as follows:
>
> *** gcc/ChangeLog ***
>
> 2017-04-11  Thomas Preud'homme  <thomas.preudhomme@arm.com>
>
>     * config/arm/iterators.md (CCSI): New mode iterator.
>     (arch): New mode attribute.
>     * config/arm/sync.md (atomic_compare_and_swap<mode>_1): Rename into ...
>     (atomic_compare_and_swap<CCSI:arch><NARROW:mode>_1): This and ...
>     (atomic_compare_and_swap<CCSI:arch><SIDI:mode>_1): This.  Use CCSI
>     code iterator for success result mode.
>     * config/arm/arm.c (arm_expand_compare_and_swap): Adapt code to use
>     the corresponding new insn generators.
>
> Testing: arm-none-eabi cross-compiler built successfully for ARMv8-M
> Mainline and Baseline without the lack of destination mode warning in
> sync.md. Testsuite show no regression.

Thanks for fixing these warnings.
The code looks ok to me but
I'd like to make sure that the rest of the arm atomic targets are not adversely affected,
so please also do a test run for ARMv7-A and ARMv8-A targets.
Also, a bootstrap is required as always.

Ok with that testing.

Thanks,
Kyrill

> Is this ok for stage4?
>
> Best regards,
>
> Thomas