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[PATCH][AArch64] Fix missing optimization for CMP+AND
- From: Sudi Das <Sudi dot Das at arm dot com>
- To: "gcc-patches at gcc dot gnu dot org" <gcc-patches at gcc dot gnu dot org>
- Cc: nd <nd at arm dot com>, Marcus Shawcroft <Marcus dot Shawcroft at arm dot com>, "Richard Earnshaw" <Richard dot Earnshaw at arm dot com>, James Greenhalgh <James dot Greenhalgh at arm dot com>
- Date: Wed, 29 Mar 2017 10:17:20 +0000
- Subject: [PATCH][AArch64] Fix missing optimization for CMP+AND
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Hi all
During combine GCC tries to merge CMP (with zero) and AND into a TST. However, in cases where an ANDS operand is not compatible, this was being missed. Adding a define_split where this operand was moved to a register seems to help out.
For example for a test :
int
f (unsigned char *p)
{
return p[0] == 50 || p[0] == 52;
}
int
g (unsigned char *p)
{
return (p[0] >> 4 & 0xfd) == 0;
}
we are now generating
f:
ldrb w0, [x0]
mov w1, 253
sub w0, w0, #50
tst w0, w1
cset w0, eq
ret
.size f, .-f
.align 2
.p2align 3,,7
.global g
.type g, %function
g:
ldrb w1, [x0]
mov w0, 13
tst w0, w1, lsr 4
cset w0, eq
ret
instead of
f:
ldrb w0, [x0]
sub w0, w0, #50
and w0, w0, -3
and w0, w0, 255
cmp w0, 0
cset w0, eq
ret
.size f, .-f
.align 2
.p2align 3,,7
.global g
.type g, %function
g:
ldrb w0, [x0]
lsr w0, w0, 4
and w0, w0, -3
cmp w0, 0
cset w0, eq
ret
Added this new test and checked for regressions on bootstrapped aarch64-none-linux-gnu
Ok for stage 1?
Thanks
Sudi
2017-03-17 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
Sudakshina Das <sudi.das@arm.com>
* config/aarch64/aarch64.md (define_split for and<mode>3nr_compare0): Move
non aarch64_logical_operand to a register.
(define_split for and_<SHIFT:optab><mode>3nr_compare0): Move non register
immediate operand to a register.
* config/aarch64/predicates.md (aarch64_mov_imm_operand): New.
2017-03-17 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
Sudakshina Das <sudi.das@arm.com>
* gcc.target/aarch64/tst_imm_split_1.c: New Test.diff --git a/gcc/config/aarch64/aarch64.md b/gcc/config/aarch64/aarch64.md
index 5adc5ed..5e5dbff 100644
--- a/gcc/config/aarch64/aarch64.md
+++ b/gcc/config/aarch64/aarch64.md
@@ -3881,6 +3881,22 @@
[(set_attr "type" "logics_reg,logics_imm")]
)
+(define_split
+ [(set (reg:CC_NZ CC_REGNUM)
+ (compare:CC_NZ
+ (and:GPI (match_operand:GPI 0 "register_operand")
+ (match_operand:GPI 1 "aarch64_mov_imm_operand"))
+ (const_int 0)))
+ (clobber (match_operand:SI 2 "register_operand"))]
+ ""
+ [(set (match_dup 2) (match_dup 1))
+ (set (reg:CC_NZ CC_REGNUM)
+ (compare:CC_NZ
+ (and:GPI (match_dup 0)
+ (match_dup 2))
+ (const_int 0)))]
+)
+
(define_insn "*and<mode>3nr_compare0_zextract"
[(set (reg:CC_NZ CC_REGNUM)
(compare:CC_NZ
@@ -3916,6 +3932,26 @@
[(set_attr "type" "logics_shift_imm")]
)
+(define_split
+ [(set (reg:CC_NZ CC_REGNUM)
+ (compare:CC_NZ
+ (and:GPI (SHIFT:GPI
+ (match_operand:GPI 0 "register_operand")
+ (match_operand:QI 1 "aarch64_shift_imm_<mode>"))
+ (match_operand:GPI 2 "aarch64_mov_imm_operand"))
+ (const_int 0)))
+ (clobber (match_operand:SI 3 "register_operand"))]
+ ""
+ [(set (match_dup 3) (match_dup 2))
+ (set (reg:CC_NZ CC_REGNUM)
+ (compare:CC_NZ
+ (and:GPI (SHIFT:GPI
+ (match_dup 0)
+ (match_dup 1))
+ (match_dup 3))
+ (const_int 0)))]
+)
+
;; -------------------------------------------------------------------
;; Shifts
;; -------------------------------------------------------------------
diff --git a/gcc/config/aarch64/predicates.md b/gcc/config/aarch64/predicates.md
index e83d45b..ed62b8e 100644
--- a/gcc/config/aarch64/predicates.md
+++ b/gcc/config/aarch64/predicates.md
@@ -106,6 +106,10 @@
(ior (match_operand 0 "register_operand")
(match_operand 0 "aarch64_logical_immediate")))
+(define_predicate "aarch64_mov_imm_operand"
+ (and (match_code "const_int")
+ (match_test "aarch64_move_imm (INTVAL (op), mode)")))
+
(define_predicate "aarch64_logical_and_immediate"
(and (match_code "const_int")
(match_test "aarch64_and_bitmask_imm (INTVAL (op), mode)")))
diff --git a/gcc/testsuite/gcc.target/aarch64/tst_imm_split_1.c b/gcc/testsuite/gcc.target/aarch64/tst_imm_split_1.c
new file mode 100644
index 0000000..33a2c0f
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/tst_imm_split_1.c
@@ -0,0 +1,18 @@
+/* { dg-do compile } */
+/* { dg-options "-O2" } */
+
+int
+f (unsigned char *p)
+{
+ return p[0] == 50 || p[0] == 52;
+}
+
+int
+g (unsigned char *p)
+{
+ return (p[0] >> 4 & 0xfd) == 0;
+}
+
+/* { dg-final { scan-assembler-not "and\\t\[xw\]\[0-9\]+, \[xw\]\[0-9\]+.*" } } */
+/* { dg-final { scan-assembler "tst\\t\[xw\]\[0-9\]+, \[xw\]\[0-9\]+" } } */
+/* { dg-final { scan-assembler "tst\\t\[xw\]\[0-9\]+, \[xw\]\[0-9\]+, lsr 4" } } */