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[PATCH] [ARC] Update ARC SIMD patterns.
- From: Claudiu Zissulescu <Claudiu dot Zissulescu at synopsys dot com>
- To: <gcc-patches at gcc dot gnu dot org>
- Cc: <Claudiu dot Zissulescu at synopsys dot com>, <Francois dot Bedard at synopsys dot com>, <andrew dot burgess at embecosm dot com>
- Date: Mon, 27 Mar 2017 13:10:12 +0200
- Subject: [PATCH] [ARC] Update ARC SIMD patterns.
- Authentication-results: sourceware.org; auth=none
Hi Andrew,
vec_select expects in selection a list of subparts. The old ARC SIMD
extension instructions were not up-to-date, update them.
Whithout this patch ARC backend is broken. It will be great if we can have it in before gcc7.x branch is cut.
Thank you,
Claudiu
gcc/
2017-03-27 Claudiu Zissulescu <claziss@synopsys.com>
* config/arc/simdext.md (vst64_insn): Update pattern.
(vld32wh_insn): Likewise.
(vld32wl_insn): Likewise.
(vld64_insn): Likewise.
(vld32_insn): Likewise.
---
gcc/config/arc/simdext.md | 98 ++++++++++++++++++++++++++++++++---------------
1 file changed, 67 insertions(+), 31 deletions(-)
diff --git a/gcc/config/arc/simdext.md b/gcc/config/arc/simdext.md
index c9ec5f4..33bb330 100644
--- a/gcc/config/arc/simdext.md
+++ b/gcc/config/arc/simdext.md
@@ -193,11 +193,16 @@
)
(define_insn "vst64_insn"
- [(set (mem:V4HI (plus:SI (zero_extend:SI (vec_select:HI (match_operand:V8HI 0 "vector_register_operand" "v")
- (parallel [(match_operand:SI 1 "immediate_operand" "L")])))
- (match_operand:SI 2 "immediate_operand" "P")))
- (vec_select:V4HI (match_operand:V8HI 3 "vector_register_operand" "=v")
- (parallel [(const_int 0)])))]
+ [(set (mem:V4HI
+ (plus:SI
+ (zero_extend:SI
+ (vec_select:HI (match_operand:V8HI 0 "vector_register_operand" "v")
+ (parallel
+ [(match_operand:SI 1 "immediate_operand" "L")])))
+ (match_operand:SI 2 "immediate_operand" "P")))
+ (vec_select:V4HI
+ (match_operand:V8HI 3 "vector_register_operand" "=v")
+ (parallel [(const_int 0) (const_int 1) (const_int 2) (const_int 3)])))]
"TARGET_SIMD_SET"
"vst64 %3, [i%1, %2]"
[(set_attr "type" "simd_vstore")
@@ -1191,12 +1196,20 @@
(set_attr "cond" "nocond")])
(define_insn "vld32wh_insn"
- [(set (match_operand:V8HI 0 "vector_register_operand" "=v")
- (vec_concat:V8HI (zero_extend:V4HI (mem:V4QI (plus:SI (match_operand:SI 1 "immediate_operand" "P")
- (zero_extend: SI (vec_select:HI (match_operand:V8HI 2 "vector_register_operand" "v")
- (parallel [(match_operand:SI 3 "immediate_operand" "L")]))))))
- (vec_select:V4HI (match_dup 0)
- (parallel [(const_int 0)]))))]
+ [(set (match_operand:V8HI 0 "vector_register_operand" "=v")
+ (vec_concat:V8HI
+ (zero_extend:V4HI
+ (mem:V4QI
+ (plus:SI
+ (match_operand:SI 1 "immediate_operand" "P")
+ (zero_extend:SI
+ (vec_select:HI
+ (match_operand:V8HI 2 "vector_register_operand" "v")
+ (parallel [(match_operand:SI 3 "immediate_operand" "L")]))))))
+ (vec_select:V4HI
+ (match_dup 0)
+ (parallel [(const_int 0) (const_int 1) (const_int 2) (const_int 3)])
+ )))]
"TARGET_SIMD_SET"
"vld32wh %0, [i%3,%1]"
[(set_attr "type" "simd_vload")
@@ -1204,12 +1217,20 @@
(set_attr "cond" "nocond")])
(define_insn "vld32wl_insn"
- [(set (match_operand:V8HI 0 "vector_register_operand" "=v")
- (vec_concat:V8HI (vec_select:V4HI (match_dup 0)
- (parallel [(const_int 1)]))
- (zero_extend:V4HI (mem:V4QI (plus:SI (match_operand:SI 1 "immediate_operand" "P")
- (zero_extend: SI (vec_select:HI (match_operand:V8HI 2 "vector_register_operand" "v")
- (parallel [(match_operand:SI 3 "immediate_operand" "L")])))))) ))]
+ [(set (match_operand:V8HI 0 "vector_register_operand" "=v")
+ (vec_concat:V8HI
+ (vec_select:V4HI
+ (match_dup 0)
+ (parallel [(const_int 4) (const_int 5) (const_int 6) (const_int 7)]))
+ (zero_extend:V4HI
+ (mem:V4QI
+ (plus:SI
+ (match_operand:SI 1 "immediate_operand" "P")
+ (zero_extend:SI
+ (vec_select:HI (match_operand:V8HI 2 "vector_register_operand" "v")
+ (parallel
+ [(match_operand:SI 3 "immediate_operand" "L")]))
+ ))))))]
"TARGET_SIMD_SET"
"vld32wl %0, [i%3,%1]"
[(set_attr "type" "simd_vload")
@@ -1229,12 +1250,19 @@
)
(define_insn "vld64_insn"
- [(set (match_operand:V8HI 0 "vector_register_operand" "=v")
- (vec_concat:V8HI (vec_select:V4HI (match_dup 0)
- (parallel [(const_int 1)]))
- (mem:V4HI (plus:SI (match_operand:SI 1 "immediate_operand" "P")
- (zero_extend: SI (vec_select:HI (match_operand:V8HI 2 "vector_register_operand" "v")
- (parallel [(match_operand:SI 3 "immediate_operand" "L")]))))) ))]
+ [(set (match_operand:V8HI 0 "vector_register_operand" "=v")
+ (vec_concat:V8HI
+ (vec_select:V4HI
+ (match_dup 0)
+ (parallel [(const_int 4) (const_int 5) (const_int 6) (const_int 7)]))
+ (mem:V4HI
+ (plus:SI
+ (match_operand:SI 1 "immediate_operand" "P")
+ (zero_extend:SI
+ (vec_select:HI
+ (match_operand:V8HI 2 "vector_register_operand" "v")
+ (parallel [(match_operand:SI 3 "immediate_operand" "L")]))
+ )))))]
"TARGET_SIMD_SET"
"vld64 %0, [i%3,%1]"
[(set_attr "type" "simd_vload")
@@ -1242,14 +1270,22 @@
(set_attr "cond" "nocond")])
(define_insn "vld32_insn"
- [(set (match_operand:V8HI 0 "vector_register_operand" "=v")
- (vec_concat:V8HI (vec_select:V4HI (match_dup 0)
- (parallel [(const_int 1)]))
- (vec_concat:V4HI (vec_select:V2HI (match_dup 0)
- (parallel [(const_int 1)]))
- (mem:V2HI (plus:SI (match_operand:SI 1 "immediate_operand" "P")
- (zero_extend: SI (vec_select:HI (match_operand:V8HI 2 "vector_register_operand" "v")
- (parallel [(match_operand:SI 3 "immediate_operand" "L")])))))) ))]
+ [(set (match_operand:V8HI 0 "vector_register_operand" "=v")
+ (vec_concat:V8HI
+ (vec_select:V4HI
+ (match_dup 0)
+ (parallel [(const_int 4) (const_int 5) (const_int 6) (const_int 7)]))
+ (vec_concat:V4HI
+ (vec_select:V2HI
+ (match_dup 0)
+ (parallel [(const_int 2) (const_int 3)]))
+ (mem:V2HI
+ (plus:SI
+ (match_operand:SI 1 "immediate_operand" "P")
+ (zero_extend:SI
+ (vec_select:HI
+ (match_operand:V8HI 2 "vector_register_operand" "v")
+ (parallel [(match_operand:SI 3 "immediate_operand" "L")]))))))))]
"TARGET_SIMD_SET"
"vld32 %0, [i%3,%1]"
[(set_attr "type" "simd_vload")
--
1.9.1