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Re: [PATCH], Add support for PowerPC ISA 3.0 vector byte reverse instructions
- From: Segher Boessenkool <segher at kernel dot crashing dot org>
- To: Michael Meissner <meissner at linux dot vnet dot ibm dot com>, gcc-patches at gcc dot gnu dot org, David Edelsohn <dje dot gcc at gmail dot com>, Bill Schmidt <wschmidt at linux dot vnet dot ibm dot com>
- Date: Wed, 18 Jan 2017 11:21:40 -0600
- Subject: Re: [PATCH], Add support for PowerPC ISA 3.0 vector byte reverse instructions
- Authentication-results: sourceware.org; auth=none
- References: <20170118015008.GA28903@ibm-tiger.the-meissners.org>
On Tue, Jan 17, 2017 at 08:50:08PM -0500, Michael Meissner wrote:
> I have checked this on a little endian power8 system (64-bit only), a big
> endian power8 system (64-bit only), and a big endian power7 system (both 32-bit
> and 64-bit), and there were no regressions. Can I check this into the trunk?
Yes please.
One comment:
> + { P9V_BUILTIN_VEC_REVB, P9V_BUILTIN_XXBRQ_V16QI,
> + RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0, 0 },
> + { P9V_BUILTIN_VEC_REVB, P9V_BUILTIN_XXBRQ_V16QI,
> + RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0, 0 },
> + { P9V_BUILTIN_VEC_REVB, P9V_BUILTIN_XXBRQ_V1TI,
> + RS6000_BTI_unsigned_V1TI, RS6000_BTI_unsigned_V1TI, 0, 0 },
> + { P9V_BUILTIN_VEC_REVB, P9V_BUILTIN_XXBRQ_V1TI,
> + RS6000_BTI_V1TI, RS6000_BTI_V1TI, 0, 0 },
> + { P9V_BUILTIN_VEC_REVB, P9V_BUILTIN_XXBRD_V2DI,
> + RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0, 0 },
> + { P9V_BUILTIN_VEC_REVB, P9V_BUILTIN_XXBRD_V2DI,
> + RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0, 0 },
> + { P9V_BUILTIN_VEC_REVB, P9V_BUILTIN_XXBRD_V2DF,
> + RS6000_BTI_V2DF, RS6000_BTI_V2DF, 0, 0 },
> + { P9V_BUILTIN_VEC_REVB, P9V_BUILTIN_XXBRW_V4SI,
> + RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0, 0 },
> + { P9V_BUILTIN_VEC_REVB, P9V_BUILTIN_XXBRW_V4SI,
> + RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0, 0 },
> + { P9V_BUILTIN_VEC_REVB, P9V_BUILTIN_XXBRW_V4SF,
> + RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0, 0 },
> + { P9V_BUILTIN_VEC_REVB, P9V_BUILTIN_XXBRH_V8HI,
> + RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0, 0 },
> + { P9V_BUILTIN_VEC_REVB, P9V_BUILTIN_XXBRH_V8HI,
> + RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0, 0 },
This is much harder to review (and read in general) than needed, because
it uses alphapetical ordering instead of something logical (like, all
integer together and ordered by size; all float together and ordered by
size).
Segher