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Re: [PATCH][AArch64] Improve SHA1 scheduling
- From: James Greenhalgh <james dot greenhalgh at arm dot com>
- To: Wilco Dijkstra <Wilco dot Dijkstra at arm dot com>
- Cc: GCC Patches <gcc-patches at gcc dot gnu dot org>, nd <nd at arm dot com>, <richard dot earnshaw at arm dot com>, <marcus dot shawcroft at arm dot com>
- Date: Tue, 17 Jan 2017 18:04:08 +0000
- Subject: Re: [PATCH][AArch64] Improve SHA1 scheduling
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On Tue, Dec 06, 2016 at 03:10:50PM +0000, Wilco Dijkstra wrote:
>
>
> ping
OK.
This has been on the list since before Stage 1 closed and should be low
risk outside of code using the SHA1H intrinsics.
Though, given where we are in the release cycle, please give
Richard/Marcus 24 hours to object before pushing it.
Thanks,
James
> From: Wilco Dijkstra
> Sent: 25 October 2016 18:08
> To: GCC Patches
> Cc: nd
> Subject: [PATCH][AArch64] Improve SHA1 scheduling
>
> SHA1H instructions may be scheduled after a SHA1C instruction
> that uses the same input register. However SHA1C updates its input,
> so if SHA1H is scheduled after it, it requires an extra move.
> Increase the priority of SHA1H to ensure it gets scheduled
> earlier, avoiding the move.
>
> Is this something the generic scheduler could do automatically for
> instructions with RMW operands?
>
> Passes bootstrap & regress. OK for commit?
>
> ChangeLog:
> 2016-10-25 Wilco Dijkstra <wdijkstr@arm.com>
>
> * config/aarch64/aarch64.c (aarch64_sched_adjust_priority)
> New function.
> (TARGET_SCHED_ADJUST_PRIORITY): Define target hook.
> --
> diff --git a/gcc/config/aarch64/aarch64.c b/gcc/config/aarch64/aarch64.c
> index 9b2f9cb19343828dc39e9950ebbefe941521942a..2b25bd1bdd6f4e7737f8e04c3b3684cdff6c4b80 100644
> --- a/gcc/config/aarch64/aarch64.c
> +++ b/gcc/config/aarch64/aarch64.c
> @@ -13668,6 +13668,26 @@ aarch64_sched_fusion_priority (rtx_insn *insn, int max_pri,
> return;
> }
>
> +/* Implement the TARGET_SCHED_ADJUST_PRIORITY hook.
> + Adjust priority of sha1h instructions so they are scheduled before
> + other SHA1 instructions. */
> +
> +static int
> +aarch64_sched_adjust_priority (rtx_insn *insn, int priority)
> +{
> + rtx x = PATTERN (insn);
> +
> + if (GET_CODE (x) == SET)
> + {
> + x = SET_SRC (x);
> +
> + if (GET_CODE (x) == UNSPEC && XINT (x, 1) == UNSPEC_SHA1H)
> + return priority + 10;
> + }
> +
> + return priority;
> +}
> +
> /* Given OPERANDS of consecutive load/store, check if we can merge
> them into ldp/stp. LOAD is true if they are load instructions.
> MODE is the mode of memory operands. */
> @@ -14431,6 +14451,9 @@ aarch64_optab_supported_p (int op, machine_mode mode1, machine_mode,
> #undef TARGET_CAN_USE_DOLOOP_P
> #define TARGET_CAN_USE_DOLOOP_P can_use_doloop_if_innermost
>
> +#undef TARGET_SCHED_ADJUST_PRIORITY
> +#define TARGET_SCHED_ADJUST_PRIORITY aarch64_sched_adjust_priority
> +
> #undef TARGET_SCHED_MACRO_FUSION_P
> #define TARGET_SCHED_MACRO_FUSION_P aarch64_macro_fusion_p
>
>
>