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Reject out-of-range bit pos in bit-fields insns operating on a register.


As seen by the testcase in PR77822, combine can generate out-of-range
bit pos in a bit-field insn, unless the pattern explicitly rejects it.
This only makes a difference for expressions that are undefined at
runtime.  Without that we would either generate bad assembler or ICE in
output_btst.

	PR target/78254
	* config/m68k/m68k.md: Reject out-of-range bit pos in bit-fields
	insns operating on a register.

Index: gcc/config/m68k/m68k.md
===================================================================
--- gcc/config/m68k/m68k.md	(revision 241995)
+++ gcc/config/m68k/m68k.md	(working copy)
@@ -706,7 +706,7 @@
 			       (minus:SI (const_int 31)
 				         (match_operand:SI 1 "general_operand" "di")))
 	     (const_int 0)))]
-  ""
+  "!(CONST_INT_P (operands[1]) && !IN_RANGE (INTVAL (operands[1]), 0, 31))"
 {
   return output_btst (operands, operands[1], operands[0], insn, 31);
 })
@@ -765,9 +765,10 @@
     (cc0)
     (compare (zero_extract:SI (match_operand:SI 0 "register_operand" "do")
 			      (const_int 1)
-			    (match_operand:SI 1 "const_int_operand" "n"))
+			      (match_operand:SI 1 "const_int_operand" "n"))
 	     (const_int 0)))]
-  "!TARGET_COLDFIRE"
+  "!TARGET_COLDFIRE
+   && !(REG_P (operands[0]) && !IN_RANGE (INTVAL (operands[1]), 0, 31))"
 {
   if (GET_CODE (operands[0]) == MEM)
     {
@@ -790,7 +791,8 @@
 			      (const_int 1)
 			      (match_operand:SI 1 "const_int_operand" "n"))
 	     (const_int 0)))]
-  "TARGET_COLDFIRE"
+  "TARGET_COLDFIRE
+   && !(REG_P (operands[0]) && !IN_RANGE (INTVAL (operands[1]), 0, 31))"
 {
   if (GET_CODE (operands[0]) == MEM)
     {
@@ -5397,6 +5399,7 @@
 			 (match_operand:SI 2 "const_int_operand" "n"))
 	(match_operand:SI 3 "register_operand" "d"))]
   "TARGET_68020 && TARGET_BITFIELD
+   && IN_RANGE (INTVAL (operands[2]), 0, 31)
    && (INTVAL (operands[1]) == 8 || INTVAL (operands[1]) == 16)
    && INTVAL (operands[2]) % INTVAL (operands[1]) == 0"
 {
@@ -5438,6 +5441,7 @@
 			 (match_operand:SI 2 "const_int_operand" "n")
 			 (match_operand:SI 3 "const_int_operand" "n")))]
   "TARGET_68020 && TARGET_BITFIELD
+   && IN_RANGE (INTVAL (operands[3]), 0, 31)
    && (INTVAL (operands[2]) == 8 || INTVAL (operands[2]) == 16)
    && INTVAL (operands[3]) % INTVAL (operands[2]) == 0"
 {
@@ -5480,6 +5484,7 @@
 			 (match_operand:SI 2 "const_int_operand" "n")
 			 (match_operand:SI 3 "const_int_operand" "n")))]
   "TARGET_68020 && TARGET_BITFIELD
+   && IN_RANGE (INTVAL (operands[3]), 0, 31)
    && (INTVAL (operands[2]) == 8 || INTVAL (operands[2]) == 16)
    && INTVAL (operands[3]) % INTVAL (operands[2]) == 0"
 {
@@ -5610,7 +5615,7 @@
 	(sign_extract:SI (match_operand:SI 1 "register_operand" "d")
 			 (match_operand:SI 2 "const_int_operand" "n")
 			 (match_operand:SI 3 "const_int_operand" "n")))]
-  "TARGET_68020 && TARGET_BITFIELD"
+  "TARGET_68020 && TARGET_BITFIELD && IN_RANGE (INTVAL (operands[3]), 0, 31)"
   "bfexts %1{%b3:%b2},%0")
 
 (define_insn "*extv_bfextu_reg"
@@ -5618,7 +5623,7 @@
 	(zero_extract:SI (match_operand:SI 1 "register_operand" "d")
 			 (match_operand:SI 2 "const_int_operand" "n")
 			 (match_operand:SI 3 "const_int_operand" "n")))]
-  "TARGET_68020 && TARGET_BITFIELD"
+  "TARGET_68020 && TARGET_BITFIELD && IN_RANGE (INTVAL (operands[3]), 0, 31)"
 {
   if (GET_CODE (operands[2]) == CONST_INT)
     {
@@ -5637,7 +5642,7 @@
 			 (match_operand:SI 1 "const_int_operand" "n")
 			 (match_operand:SI 2 "const_int_operand" "n"))
 	(const_int 0))]
-  "TARGET_68020 && TARGET_BITFIELD"
+  "TARGET_68020 && TARGET_BITFIELD && IN_RANGE (INTVAL (operands[2]), 0, 31)"
 {
   CC_STATUS_INIT;
   return "bfclr %0{%b2:%b1}";
@@ -5648,7 +5653,7 @@
 			 (match_operand:SI 1 "const_int_operand" "n")
 			 (match_operand:SI 2 "const_int_operand" "n"))
 	(const_int -1))]
-  "TARGET_68020 && TARGET_BITFIELD"
+  "TARGET_68020 && TARGET_BITFIELD && IN_RANGE (INTVAL (operands[2]), 0, 31)"
 {
   CC_STATUS_INIT;
   return "bfset %0{%b2:%b1}";
@@ -5659,7 +5664,7 @@
 			 (match_operand:SI 1 "const_int_operand" "n")
 			 (match_operand:SI 2 "const_int_operand" "n"))
 	(match_operand:SI 3 "register_operand" "d"))]
-  "TARGET_68020 && TARGET_BITFIELD"
+  "TARGET_68020 && TARGET_BITFIELD && IN_RANGE (INTVAL (operands[2]), 0, 31)"
 {
 #if 0
   /* These special cases are now recognized by a specific pattern.  */
@@ -5707,7 +5712,8 @@
 				  (match_operand:SI 1 "const_int_operand" "n")
 			 	  (match_operand:SI 2 "general_operand" "dn"))
 		 (const_int 0)))]
-  "TARGET_68020 && TARGET_BITFIELD"
+  "TARGET_68020 && TARGET_BITFIELD
+    && !(CONST_INT_P (operands[2]) && !IN_RANGE (INTVAL (operands[2]), 0, 31))"
 {
   if (operands[1] == const1_rtx
       && GET_CODE (operands[2]) == CONST_INT)

-- 
Andreas Schwab, SUSE Labs, schwab@suse.de
GPG Key fingerprint = 0196 BAD8 1CE9 1970 F4BE  1748 E4D4 88E3 0EEA B9D7
"And now for something completely different."


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