Re: [PATCH PR69848]Avoid not insn by inverting comparison code in vcond patterns

["Bin.Cheng" <amker dot cheng at gmail dot com>]

On Tue, Aug 16, 2016 at 10:53 AM, James Greenhalgh
<james.greenhalgh@arm.com> wrote:
> On Wed, Aug 10, 2016 at 04:00:16PM +0000, Bin Cheng wrote:
>> Hi,
>> This is a follow up patch for previous vcond patches.  In previous ones,
>> we rely on combiner to simplify "X = !Y; Z = X ? A : B" into "Z = Y ? B : A".
>> That works for some cases, but not all of them, for example, case in
>> PR69848.  The reason could be in combiner, but more likely in bsl patterns
>> which are too complicated to be handled by combiner.  Investigating all
>> cases pattern by pattern would be tedious, this patch modifies vcond
>> patterns to explicitly invert comparison code (as well as switch operands)
>> to avoid the additional NOT instruction.  Note un-ordered floating point
>> comparison is not handled because it will complicate the code, also NE is
>> the most common case.  The patch further reduces assembly code in
>> PR69848 on the basis of vcond patches.
>> Bootstrap and test on AArch64.  Is it OK?
>
> OK for trunk.
>
> It would be good to reduce some of the code duplication we have in
> these vcond patterns. Right now we have 4 copies of essentially
> identical code.
Thanks for reviewing.  The duplication of vcond patterns is because of
mixed types between comparison and cond_expr.  Unless we can merge the
two vec_cmp patterns, I don't have idea at the moment.  On the other
hand, vec_cmp code which is largely copied from previous vcond
patterns could be improved using operator iterator.
I will apply this one later.

Thanks,
bin
>
> Thanks,
> James
>