[PATCH PR69848]Avoid not insn by inverting comparison code in vcond patterns

[Bin Cheng <Bin dot Cheng at arm dot com>]

Hi,
This is a follow up patch for previous vcond patches.  In previous ones, 
we rely on combiner to simplify "X = !Y; Z = X ? A : B" into "Z = Y ? B : A".
That works for some cases, but not all of them, for example, case in 
PR69848.  The reason could be in combiner, but more likely in bsl patterns
which are too complicated to be handled by combiner.  Investigating all
cases pattern by pattern would be tedious, this patch modifies vcond 
patterns to explicitly invert comparison code (as well as switch operands)
to avoid the additional NOT instruction.  Note un-ordered floating point 
comparison is not handled because it will complicate the code, also NE is 
the most common case.  The patch further reduces assembly code in 
PR69848 on the basis of vcond patches.
Bootstrap and test on AArch64.  Is it OK?

Thanks,
bin

2016-08-03  Bin Cheng  <bin.cheng@arm.com>

	PR tree-optimization/69848
	* config/aarch64/aarch64-simd.md (vcond<mode><mode>): Invert NE
	and swtich operands to avoid additional NOT instruction.
	(vcond<v_cmp_mixed><mode>): Ditto.
	(vcondu<mode><mode>, vcondu<mode><v_cmp_mixed>): Ditto.

gcc/testsuite/ChangeLog
2016-08-03  Bin Cheng  <bin.cheng@arm.com>

	PR tree-optimization/69848
	* gcc.target/aarch64/simd/vcond-ne-bit.c: New test.

Attachment: avoid-not-insn-in-vcond-20160803.txt
Description: avoid-not-insn-in-vcond-20160803.txt