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[PATCH 2/3][AArch64] Improve zero extend
- From: Wilco Dijkstra <Wilco dot Dijkstra at arm dot com>
- To: GCC Patches <gcc-patches at gcc dot gnu dot org>
- Cc: nd <nd at arm dot com>, James Greenhalgh <James dot Greenhalgh at arm dot com>
- Date: Tue, 19 Jul 2016 15:31:46 +0000
- Subject: [PATCH 2/3][AArch64] Improve zero extend
- Authentication-results: sourceware.org; auth=none
- Nodisclaimer: True
- Spamdiagnosticmetadata: NSPM
- Spamdiagnosticoutput: 1:99
When zero extending a 32-bit value to 64 bits, there should always be a
SET operation on the outside, according to the patterns in aarch64.md.
However, the mid-end can also ask for the cost of a made-up instruction,
where the zero-extend is part of another operation, not SET.
In this case we currently cost the zero extend operation as a uxtb/uxth.
Instead, cost it the same way we cost "normal" 32-to-64-bit zero
extends: as a "mov" or the cost of the inner operation.
Bootstrapped and tested on aarch64-none-elf.
2016-07-19 Kristina Martsenko <kristina.martsenko@arm.com>
* config/aarch64/aarch64.c (aarch64_rtx_costs): Fix cost of zero extend.
---
gcc/config/aarch64/aarch64.c | 5 ++---
1 file changed, 2 insertions(+), 3 deletions(-)
diff --git a/gcc/config/aarch64/aarch64.c b/gcc/config/aarch64/aarch64.c
index bddffc3ab28cde3a996fd13c060de36227315fb5..a2621313d3278d39db0f1d5640b33201efefac21 100644
--- a/gcc/config/aarch64/aarch64.c
+++ b/gcc/config/aarch64/aarch64.c
@@ -6421,12 +6421,11 @@ cost_plus:
a 'w' register implicitly zeroes the upper bits of an 'x'
register. However, if this is
- (set (reg) (zero_extend (reg)))
+ (zero_extend (reg))
we must cost the explicit register move. */
if (mode == DImode
- && GET_MODE (op0) == SImode
- && outer == SET)
+ && GET_MODE (op0) == SImode)
{
int op_cost = rtx_cost (op0, VOIDmode, ZERO_EXTEND, 0, speed);
--
2.1.4