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[v2][AArch64, 3/6] Reimplement frsqrte intrinsics
- From: Jiong Wang <jiong dot wang at foss dot arm dot com>
- To: James Greenhalgh <james dot greenhalgh at arm dot com>
- Cc: GCC Patches <gcc-patches at gcc dot gnu dot org>
- Date: Mon, 6 Jun 2016 14:40:22 +0100
- Subject: [v2][AArch64, 3/6] Reimplement frsqrte intrinsics
- Authentication-results: sourceware.org; auth=none
- References: <57430251 dot 6060902 at foss dot arm dot com> <57440F88 dot 2060603 at foss dot arm dot com> <20160527130344 dot GF26495 at arm dot com> <57487B41 dot 8020200 at foss dot arm dot com> <6af07de4-8179-c0bf-410c-317ef52876dd at foss dot arm dot com> <7cb1e234-46f9-76b4-aefd-1eacabfb4ca7 at foss dot arm dot com>
These intrinsics were implemented before the instruction pattern
"aarch64_rsqrte<mode>" added, that these intrinsics were implemented through
inline assembly.
This mirgrate the implementation to builtin.
gcc/
2016-06-06 Jiong Wang<jiong.wang@arm.com>
* config/aarch64/aarch64-builtins.def (rsqrte): New builtins for modes
VALLF.
* config/aarch64/aarch64-simd.md (aarch64_rsqrte_<mode>2): Rename to
"aarch64_rsqrte<mode>".
* config/aarch64/aarch64.c (get_rsqrte_type): Update gen* name.
* config/aarch64/arm_neon.h (vrsqrts_f32): Remove inline assembly. Use
builtin.
(vrsqrted_f64): Likewise.
(vrsqrte_f32): Likewise.
(vrsqrte_f64): Likewise.
(vrsqrteq_f32): Likewise.
(vrsqrteq_f64): Likewise.
diff --git a/gcc/config/aarch64/aarch64-simd-builtins.def b/gcc/config/aarch64/aarch64-simd-builtins.def
index 25a5270766401bd2f31ccacdafee83c183bdf775..f60f84c42fefd32bace6f4aa690f97ca54f3e4b6 100644
--- a/gcc/config/aarch64/aarch64-simd-builtins.def
+++ b/gcc/config/aarch64/aarch64-simd-builtins.def
@@ -451,3 +451,6 @@
BUILTIN_VALLI (BINOP_SUS, ucvtf, 3)
BUILTIN_VALLF (BINOP, fcvtzs, 3)
BUILTIN_VALLF (BINOP_USS, fcvtzu, 3)
+
+ /* Implemented by aarch64_rsqrte<mode>. */
+ BUILTIN_VALLF (UNOP, rsqrte, 0)
diff --git a/gcc/config/aarch64/aarch64-simd.md b/gcc/config/aarch64/aarch64-simd.md
index ca90b666a7e3888057b7d9e8562a2544a006cf0f..941214680262ef1015cbb23f518b4999f962bf9b 100644
--- a/gcc/config/aarch64/aarch64-simd.md
+++ b/gcc/config/aarch64/aarch64-simd.md
@@ -382,7 +382,7 @@
[(set_attr "type" "neon<fp>_mul_<Vetype>_scalar<q>")]
)
-(define_insn "aarch64_rsqrte_<mode>2"
+(define_insn "aarch64_rsqrte<mode>"
[(set (match_operand:VALLF 0 "register_operand" "=w")
(unspec:VALLF [(match_operand:VALLF 1 "register_operand" "w")]
UNSPEC_RSQRTE))]
diff --git a/gcc/config/aarch64/aarch64.c b/gcc/config/aarch64/aarch64.c
index ad07fe196a814ace78d43f66e70280d20a4476b5..acfb39dc025d74fe531d439bb87c52d18955ee7c 100644
--- a/gcc/config/aarch64/aarch64.c
+++ b/gcc/config/aarch64/aarch64.c
@@ -7349,11 +7349,11 @@ get_rsqrte_type (machine_mode mode)
{
switch (mode)
{
- case DFmode: return gen_aarch64_rsqrte_df2;
- case SFmode: return gen_aarch64_rsqrte_sf2;
- case V2DFmode: return gen_aarch64_rsqrte_v2df2;
- case V2SFmode: return gen_aarch64_rsqrte_v2sf2;
- case V4SFmode: return gen_aarch64_rsqrte_v4sf2;
+ case DFmode: return gen_aarch64_rsqrtedf;
+ case SFmode: return gen_aarch64_rsqrtesf;
+ case V2DFmode: return gen_aarch64_rsqrtev2df;
+ case V2SFmode: return gen_aarch64_rsqrtev2sf;
+ case V4SFmode: return gen_aarch64_rsqrtev4sf;
default: gcc_unreachable ();
}
}
diff --git a/gcc/config/aarch64/arm_neon.h b/gcc/config/aarch64/arm_neon.h
index 04bce9ab80c151877619ee75e7cb50f5951099f7..e4f7a66abcc59f306de289d22e9d09cfe32c0c87 100644
--- a/gcc/config/aarch64/arm_neon.h
+++ b/gcc/config/aarch64/arm_neon.h
@@ -9163,28 +9163,6 @@ vqrdmulhq_n_s32 (int32x4_t a, int32_t b)
result; \
})
-__extension__ static __inline float32x2_t __attribute__ ((__always_inline__))
-vrsqrte_f32 (float32x2_t a)
-{
- float32x2_t result;
- __asm__ ("frsqrte %0.2s,%1.2s"
- : "=w"(result)
- : "w"(a)
- : /* No clobbers */);
- return result;
-}
-
-__extension__ static __inline float64x1_t __attribute__ ((__always_inline__))
-vrsqrte_f64 (float64x1_t a)
-{
- float64x1_t result;
- __asm__ ("frsqrte %d0,%d1"
- : "=w"(result)
- : "w"(a)
- : /* No clobbers */);
- return result;
-}
-
__extension__ static __inline uint32x2_t __attribute__ ((__always_inline__))
vrsqrte_u32 (uint32x2_t a)
{
@@ -9196,39 +9174,6 @@ vrsqrte_u32 (uint32x2_t a)
return result;
}
-__extension__ static __inline float64_t __attribute__ ((__always_inline__))
-vrsqrted_f64 (float64_t a)
-{
- float64_t result;
- __asm__ ("frsqrte %d0,%d1"
- : "=w"(result)
- : "w"(a)
- : /* No clobbers */);
- return result;
-}
-
-__extension__ static __inline float32x4_t __attribute__ ((__always_inline__))
-vrsqrteq_f32 (float32x4_t a)
-{
- float32x4_t result;
- __asm__ ("frsqrte %0.4s,%1.4s"
- : "=w"(result)
- : "w"(a)
- : /* No clobbers */);
- return result;
-}
-
-__extension__ static __inline float64x2_t __attribute__ ((__always_inline__))
-vrsqrteq_f64 (float64x2_t a)
-{
- float64x2_t result;
- __asm__ ("frsqrte %0.2d,%1.2d"
- : "=w"(result)
- : "w"(a)
- : /* No clobbers */);
- return result;
-}
-
__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__))
vrsqrteq_u32 (uint32x4_t a)
{
@@ -9240,17 +9185,6 @@ vrsqrteq_u32 (uint32x4_t a)
return result;
}
-__extension__ static __inline float32_t __attribute__ ((__always_inline__))
-vrsqrtes_f32 (float32_t a)
-{
- float32_t result;
- __asm__ ("frsqrte %s0,%s1"
- : "=w"(result)
- : "w"(a)
- : /* No clobbers */);
- return result;
-}
-
__extension__ static __inline float32x2_t __attribute__ ((__always_inline__))
vrsqrts_f32 (float32x2_t a, float32x2_t b)
{
@@ -21504,6 +21438,44 @@ vrshrd_n_u64 (uint64_t __a, const int __b)
return __builtin_aarch64_urshr_ndi_uus (__a, __b);
}
+/* vrsqrte. */
+
+__extension__ static __inline float32_t __attribute__ ((__always_inline__))
+vrsqrtes_f32 (float32_t __a)
+{
+ return __builtin_aarch64_rsqrtesf (__a);
+}
+
+__extension__ static __inline float64_t __attribute__ ((__always_inline__))
+vrsqrted_f64 (float64_t __a)
+{
+ return __builtin_aarch64_rsqrtedf (__a);
+}
+
+__extension__ static __inline float32x2_t __attribute__ ((__always_inline__))
+vrsqrte_f32 (float32x2_t __a)
+{
+ return __builtin_aarch64_rsqrtev2sf (__a);
+}
+
+__extension__ static __inline float64x1_t __attribute__ ((__always_inline__))
+vrsqrte_f64 (float64x1_t __a)
+{
+ return (float64x1_t) {vrsqrted_f64 (vget_lane_f64 (__a, 0))};
+}
+
+__extension__ static __inline float32x4_t __attribute__ ((__always_inline__))
+vrsqrteq_f32 (float32x4_t __a)
+{
+ return __builtin_aarch64_rsqrtev4sf (__a);
+}
+
+__extension__ static __inline float64x2_t __attribute__ ((__always_inline__))
+vrsqrteq_f64 (float64x2_t __a)
+{
+ return __builtin_aarch64_rsqrtev2df (__a);
+}
+
/* vrsra */
__extension__ static __inline int8x8_t __attribute__ ((__always_inline__))