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GCC 6.1 added support for the XXPERM instruction for the PowerPC ISA 3.0. The XXPERM instruction is essentially a 4 operand instruction, with only 3 operands in the instruction (the target register overlaps with the first input register). The Power9 hardware has fusion support where if the instruction that precedes the XXPERM is a XXLOR move instruction to set the first input argument, it is fused with the XXPERM. I added code to support this fusion. Unfortunately, in running the testsuite on the power9 simulator, we discovered that the test gcc.c-torture/execute/pr56866.c would fail because the fusion alternatives confused the register allocator and/or the passes after the register allocator. This patch removes the explicit fusion support from XXPERM. In addition, ISA 3.0 added XXPERMR and VPERMR instructions for little endian support where the permute vector reverses the bytes. This patch adds support for XXPERMR/VPERMR. [gcc] 2016-05-19 Michael Meissner <meissner@linux.vnet.ibm.com> Kelvin Nilsen <kelvin@gcc.gnu.org> PR target/71201 * config/rs6000/rs6000.c (rs6000_expand_vector_set): Generate vpermr/xxpermr on ISA 3.0. (altivec_expand_vec_perm_le): Likewise. * config/rs6000/altivec.md (UNSPEC_VPERMR): New unspec. (altivec_vperm_<mode>_internal): Drop ISA 3.0 xxperm fusion alternative. (altivec_vperm_v8hiv16qi): Likewise. (altivec_vperm_<mode>_uns_internal): Likewise. (vperm_v8hiv4si): Likewise. (vperm_v16qiv8hi): Likewise. (altivec_vpermr_<mode>_internal): Add VPERMR/XXPERMR support for ISA 3.0. [gcc/testsuite] 2016-05-19 Michael Meissner <meissner@linux.vnet.ibm.com> Kelvin Nilsen <kelvin@gcc.gnu.org> * gcc.target/powerpc/p9-permute.c: Run test on big endian as well as little endian. * gcc.target/powerpc/p9-vpermr.c: New test for ISA 3.0 vpermr support. -- Michael Meissner, IBM IBM, M/S 2506R, 550 King Street, Littleton, MA 01460-6245, USA email: meissner@linux.vnet.ibm.com, phone: +1 (978) 899-4797
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