[PATCH][AArch64][wwwdocs] Summarise some more AArch64 changes for GCC6

[Kyrill Tkachov <kyrylo dot tkachov at foss dot arm dot com>]

Hi all,

Here's a proposed summary of the changes in the AArch64 backend for GCC 6.
If there's anything I've missed it's purely my oversight, feel free to add
entries or suggest improvements.

Jim, you added support for the qdf24xx identifier to -mcpu and -mtune.
Could you please suggest an appropriate entry to describe it?
I think the same format as the Cortex-A35 entry in this patch would be appropriate.

Ok to commit?

Thanks,
Kyrill

Index: htdocs/gcc-6/changes.html
===================================================================
RCS file: /cvs/gcc/wwwdocs/htdocs/gcc-6/changes.html,v
retrieving revision 1.62
diff -U 3 -r1.62 changes.html
--- htdocs/gcc-6/changes.html	24 Feb 2016 09:36:06 -0000	1.62
+++ htdocs/gcc-6/changes.html	12 Apr 2016 12:47:30 -0000
@@ -312,29 +312,91 @@
 <h3 id="aarch64">AArch64</h3>
    <ul>
      <li>
+       A number of AArch64-specific options were added.  The most important
+       ones are summarised in this section but for usage instructions please
+       refer to the documentation.
+     </li>
+     <li>
        The new command line options <code>-march=native</code>,
        <code>-mcpu=native</code> and <code>-mtune=native</code> are now
        available on native AArch64 GNU/Linux systems.  Specifying
        these options will cause GCC to auto-detect the host CPU and
        rewrite these options to the optimal setting for that system.
-       If GCC is unable to detect the host CPU these options have no effect.
      </li>
      <li>
-       <code>-fpic</code> is now supported by the AArch64 target when generating
+       <code>-fpic</code> is now supported when generating
        code for the small code model (<code>-mcmodel=small</code>).  The size of
        the global offset table (GOT) is limited to 28KiB under the LP64 SysV ABI
        , and 15KiB under the ILP32 SysV ABI.
      </li>
      <li>
-       The AArch64 port now supports target attributes and pragmas.  Please
-       refer to the <a href="https://gcc.gnu.org/onlinedocs/gcc/AArch64-Function-Attributes.html#AArch64-Function-Attributes";>
-       documentation</a> for details of available attributes and
+       Target attributes and pragmas are now supported.  Please
+       refer to the documentation for details of available attributes and
        pragmas as well as usage instructions.
      </li>
      <li>
        Link-time optimization across translation units with different
        target-specific options is now supported.
      </li>
+     <li>
+       The option <code>-mtls-size=</code> is now supported.  It can be used to
+       specify the bit size of TLS offsets, allowing GCC to generate
+       better TLS instruction sequences.
+     </li>
+     <li>
+       The option <code>-fno-plt</code> is now fixed and is fully
+       functional.
+     </li>
+     <li>
+       The ARMv8.1-A architecture and the Large System Extensions are now
+       supported.  They can be used by specifying the
+       <code>-march=armv8.1-a</code> option.  Additionally, the
+       <code>+lse</code> option extension can be used in a similar fashion
+       to other option extensions.
+       The Large System Extensions introduce new instructions that are used
+       in the implementation of common atomic operations.
+     </li>
+     <li>
+       The ACLE half-precision floating-point type <code>__fp16</code> is now
+       supported in the C and C++ languages.
+     </li>
+     <li>
+       The ARM Cortex-A35 processor is now supported via the
+       <code>-mcpu=cortex-a35</code> and <code>-mtune=cortex-a35</code>
+       options as well as the equivalent target attributes and pragmas.
+     </li>
+     <li>
+       Code generation for the ARM Cortex-A57 processor is improved.
+       Among general code generation improvements, a better algorithm is
+       added for allocating registers to floating-point multiply-accumulate
+       instructions offering increased performance when compiling with
+       <code>-mcpu=cortex-a57</code> or <code>-mtune=cortex-a57</code>.
+     </li>
+     <li>Code generation for the ARM Cortex-A53 processor is improved.
+       A more accurate instruction scheduling model for the processor is
+       now used, and a number of compiler tuning parameters have been set
+       to offer increased performance when compiling with
+       <code>-mcpu=cortex-a53</code> or <code>-mtune=cortex-a53</code>.
+     </li>
+     <li>Code generation for the Samsung Exynos M1 processor is improved.
+       A more accurate instruction scheduling model for the processor is
+       now used, and a number of compiler tuning parameters have been set
+       to offer increased performance when compiling with
+       <code>-mcpu=exynos-m1</code> or <code>-mtune=exynos-m1</code>.
+     </li>
+     <li>
+       Improvements in the generation of conditional branches and literal
+       pools were made to allow the compiler to compile functions of a large
+       size.  Constant pools are now placed into separate rodata sections.
+       The new option <code>-mpc-relative-literal-loads</code> is
+       introduced to generate per-function literal pools, limiting the maximum
+       size of functions to 1MiB.
+     </li>
+     <li>
+       Several correctness issues with generation of Advanced SIMD instructions
+       for big-endian targets have been fixed resulting in improved code
+       generation for ACLE intrinsics with <code>-mbig-endian</code>.
+     </li>
    </ul>
 
 <h3 id="arm">ARM</h3>