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Re: [PATCH] [AArch64] support -mfentry feature for arm64
- From: Michael Matz <matz at suse dot de>
- To: Andrew Haley <aph at redhat dot com>
- Cc: gcc-patches at gcc dot gnu dot org
- Date: Tue, 19 Apr 2016 15:19:03 +0200 (CEST)
- Subject: Re: [PATCH] [AArch64] support -mfentry feature for arm64
- Authentication-results: sourceware.org; auth=none
- References: <1457943260-30894-1-git-send-email-huawei dot libin at huawei dot com> <B6E2AECD-096C-489F-A217-8140E781E722 at linaro dot org> <alpine dot LSU dot 2 dot 20 dot 1604151739210 dot 20277 at wotan dot suse dot de> <alpine dot LNX dot 2 dot 20 dot 1604152026570 dot 26109 at monopod dot intra dot ispras dot ru> <5714F001 dot 8090408 at redhat dot com> <alpine dot LSU dot 2 dot 20 dot 1604181910520 dot 20277 at wotan dot suse dot de> <57151699 dot 6020602 at redhat dot com> <alpine dot LSU dot 2 dot 20 dot 1604181929170 dot 20277 at wotan dot suse dot de> <5715E5A9 dot 8060500 at redhat dot com>
Hi,
On Tue, 19 Apr 2016, Andrew Haley wrote:
> > I will happily declare any implementation where it's impossible to
> > safely patch the instruction stream by flushing the respective buffers
> > or other means completely under control of the patching machinery, to
> > be broken by design.
>
> You can declare anything you want, but we have to program for the
> architectural specification.
>
> > What failure mode do you envision, exactly?
>
> It's easiest just to quote from the spec:
>
> How far ahead of the current point of execution instructions are
> fetched from is IMPLEMENTATION DEFINED. Such prefetching can be
> either a fixed or a dynamically varying number of instructions,
> and can follow any or all possible future execution paths. For all
> types of memory:
>
> The PE might have fetched the instructions from memory at any
> time since the last Context synchronization operation on that
> PE.
>
> Any instructions fetched in this way might be executed multiple
> times, if this is required by the execution of the program,
> without being re-fetched from memory. In the absence of an ISB,
> there is no limit on the number of times such an instruction
> might be executed without being re-fetched from memory.
>
> The ARM architecture does not require the hardware to ensure
> coherency between instruction caches and memory, even for
> locations of shared memory.
Well, yeah, that's traditional insn caches on multiple cores. From user
space you need kernel help for this, doing interprocess interrupts to
flush all such buffers on all cores (or at least those potentially
fetching stuff in the patched region, if such granularity is possible).
An implementation providing such is non-broken :) Alternatively the
various invalidate cache instructions need to have a form that invalidates
the i$ on all cores.
That's just normal code patching on multi-core systems. Nothing specific
for aarch64 and nothing the GCC side needs to cater for.
> I have wondered if it might be a good idea to use an inter-processor
> interrupt to force a context synchronization event across all PEs.
So, this, exactly.
Ciao,
Michael.