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Re: [PATCH][ARM] PR target/70566 Check that condition register is dead in tst-imm -> lsls-imm Thumb2 peepholes
- From: "Richard Earnshaw (lists)" <Richard dot Earnshaw at arm dot com>
- To: Kyrill Tkachov <kyrylo dot tkachov at foss dot arm dot com>, GCC Patches <gcc-patches at gcc dot gnu dot org>
- Cc: Ramana Radhakrishnan <ramana dot radhakrishnan at arm dot com>
- Date: Tue, 12 Apr 2016 10:12:04 +0100
- Subject: Re: [PATCH][ARM] PR target/70566 Check that condition register is dead in tst-imm -> lsls-imm Thumb2 peepholes
- Authentication-results: sourceware.org; auth=none
- References: <570673FB dot 7020803 at foss dot arm dot com> <57077A47 dot 2070100 at arm dot com> <570BA628 dot 4070606 at foss dot arm dot com>
On 11/04/16 14:27, Kyrill Tkachov wrote:
>
> On 08/04/16 10:30, Richard Earnshaw (lists) wrote:
>> On 07/04/16 15:51, Kyrill Tkachov wrote:
>>> Hi all,
>>>
>>> In this wrong-code PR we have a Thumb2 peephole transforming:
>>> tst r3, #2
>>> bne .L3
>>> beq .L6
>>>
>>> into:
>>> lsls r3, r3, #30 // LSLS is shorter than TST in Thumb2
>>> bmi .L3
>>> beq .L6
>>>
>>> that is, the branch following the extract+compare has its condition
>>> properly changed but the
>>> following branch doesn't get updated to check the opposite condition of
>>> MI (PL).
>>> Since the peepholes in thumb2.md only see the compare and a single
>>> branch the solution,
>>> suggested by Richard, is to guard those peepholes on the condition that
>>> the condition register
>>> is dead after the first branch. This patch does that and with it we no
>>> longer perform the transformation
>>> on the testcase. I've checked manually that we still perform the
>>> peephole when the condition register
>>> is indeed dead after the sequence.
>>>
>>> Bootstrapped and tested on on arm-none-linux-gnueabihf with
>>> --with-mode=thumb as this affects only
>>> Thumb2 codegen.
>>>
>>> Ok for trunk?
>>>
>>> This PR also affects GCC 5 and 4.9 so I'll be testing the patch there as
>>> well.
>>>
>>> Thanks,
>>> Kyrill
>>>
>>>
>>> 2016-04-07 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
>>>
>>> PR target/70566
>>> * config/arm/thumb2.md (tst + branch-> lsls + branch
>>> peephole below *orsi_not_shiftsi_si): Require that condition
>>> register is dead after the peephole.
>>> (second peephole after the above): Likewise.
>>>
>>> 2016-04-07 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
>>>
>>> PR target/70566
>>> * gcc.c-torture/execute/pr70566.c: New test.
>>
>> OK.
>
> Thanks, the patch has passed bootstrap and test on the GCC 5 and 4.9
> branches. Is it ok to backport it there as well?
>
OK by me.
R.
> Thanks,
> Kyrill
>
>>
>> R.
>