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Re: [PATCH][PR rtl-optimization/69307] Handle hard registers in modes that span more than one register properly

Hello Jeff,

On 12.03.2016 20:13, Jeff Law wrote:


As Andrey outlined in the PR, selective-scheduling was missing a check &
handling of hard registers in modes that span more than one hard reg. This
caused an incorrect register selection during renaming.

I verified removing the printf call from the test would not compromise the
test.  Then I did a normal x86 bootstrap & regression test with the patch.
Of course that's essentially useless, so I also did another bootstrap and
regression test with -fselective-scheduling in BOOT_CFLAGS with and without
this patch.  In both cases there were no regressions.
Thank you for checking this in. I've also tested this patch in the similar way (forcing selective scheduling for 2nd and both schedulers) both on x86-64 and ia64. I've posted the patches for remaining sel-sched PRs just now -- it took some time bringing our Itaniums back to life. 

Andrey



I'm installing Andrey's patch on the trunk.  I'm not sure this is worth
addressing in gcc-5.

Jeff
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