Re: [PATCH, ARM] Fix gcc.c-torture/execute/loop-2b.c execution failure on cortex-m0

[Thomas Preudhomme <thomas dot preudhomme at foss dot arm dot com>]

On Friday 15 January 2016 12:45:04 Ramana Radhakrishnan wrote:
> On Wed, Dec 16, 2015 at 9:11 AM, Thomas Preud'homme
> 
> <thomas.preudhomme@foss.arm.com> wrote:
> > During reorg pass, thumb1_reorg () is tasked with rewriting mov rd, rn to
> > subs rd, rn, 0 to avoid a comparison against 0 instruction before doing a
> > conditional branch based on it. The actual avoiding of cmp is done in
> > cbranchsi4_insn instruction C output template. When the condition is met,
> > the source register (rn) is also propagated into the comparison in place
> > the destination register (rd).
> > 
> > However, right now thumb1_reorg () only look for a mov followed by a
> > cbranchsi but does not check whether the comparison in cbranchsi is
> > against the constant 0. This is not safe because a non clobbering
> > instruction could exist between the mov and the comparison that modifies
> > the source register. This is what happens here with a post increment of
> > the source register after the mov, which skip the &a[i] == &a[1]
> > comparison for iteration i == 1.
> > 
> > This patch fixes the issue by checking that the comparison is against
> > constant 0.
> > 
> > ChangeLog entry is as follow:
> > 
> > 
> > *** gcc/ChangeLog ***
> > 
> > 2015-12-07  Thomas Preud'homme  <thomas.preudhomme@arm.com>
> > 
> >         * config/arm/arm.c (thumb1_reorg): Check that the comparison is
> >         against the constant 0.
> 
> OK.
> 
> Ramana
> 
> > diff --git a/gcc/config/arm/arm.c b/gcc/config/arm/arm.c
> > index 42bf272..49c0a06 100644
> > --- a/gcc/config/arm/arm.c
> > +++ b/gcc/config/arm/arm.c
> > @@ -17195,7 +17195,7 @@ thumb1_reorg (void)
> > 
> >    FOR_EACH_BB_FN (bb, cfun)
> >    
> >      {
> >      
> >        rtx dest, src;
> > 
> > -      rtx pat, op0, set = NULL;
> > +      rtx cmp, op0, op1, set = NULL;
> > 
> >        rtx_insn *prev, *insn = BB_END (bb);
> >        bool insn_clobbered = false;
> > 
> > @@ -17208,8 +17208,13 @@ thumb1_reorg (void)
> > 
> >         continue;
> >        
> >        /* Get the register with which we are comparing.  */
> > 
> > -      pat = PATTERN (insn);
> > -      op0 = XEXP (XEXP (SET_SRC (pat), 0), 0);
> > +      cmp = XEXP (SET_SRC (PATTERN (insn)), 0);
> > +      op0 = XEXP (cmp, 0);
> > +      op1 = XEXP (cmp, 1);
> > +
> > +      /* Check that comparison is against ZERO.  */
> > +      if (!CONST_INT_P (op1) || INTVAL (op1) != 0)
> > +       continue;
> > 
> >        /* Find the first flag setting insn before INSN in basic block BB. 
> >        */
> >        gcc_assert (insn != BB_HEAD (bb));
> > 
> > @@ -17249,7 +17254,7 @@ thumb1_reorg (void)
> > 
> >           PATTERN (prev) = gen_rtx_SET (dest, src);
> >           INSN_CODE (prev) = -1;
> >           /* Set test register in INSN to dest.  */
> > 
> > -         XEXP (XEXP (SET_SRC (pat), 0), 0) = copy_rtx (dest);
> > +         XEXP (cmp, 0) = copy_rtx (dest);
> > 
> >           INSN_CODE (insn) = -1;
> >         
> >         }
> >      
> >      }
> > 
> > Testsuite shows no regression when run for arm-none-eabi with
> > -mcpu=cortex-m0 -mthumb

The patch applies cleanly on gcc-5-branch and also show no regression when run 
for arm-none-eabi with -mcpu=cortex-m0 -mthumb. Is it ok to backport?

Best regards,

Thomas