Re: [PATCH], Add power9 support to GCC, patch #10 (SFmode/DFmode d-form addressing)

[David Edelsohn <dje dot gcc at gmail dot com>]

On Tue, Nov 10, 2015 at 4:56 PM, Michael Meissner
<meissner@linux.vnet.ibm.com> wrote:
> This patch d-form addressing to float/double scalars for the PowerPC that was
> added in ISA 3.0 (power9).  This patch does not yet turn on D-form addressing
> as default.  It is likely that patch #11, which will add limited d-form
> addressing to vector registers will enable it by default.
>
> I have bootstrapped the compiler with these changes, and there were no
> regressions to the testsuite.
>
> In addition, I built all of the Spec 2006 benchmark with my normal options
> (-ffast-math -O3 -mveclibabi=mass -mcpu=power9 -mpower9-dform -mrecip=rsqrt
> -fpeel-loops -funroll-loops -fvect-cost-model -msave-toc-indirect
> -fno-aggressive-loop-optimizations -mno-pointers-to-nested-functions) and there
> were no compiler failures (and various power9 instructions were generated,
> including d-form addressing).
>
> Are these patches ok to check in?
>
> [gcc]
> 2015-11-10  Michael Meissner  <meissner@linux.vnet.ibm.com>
>
>         <patch #10>
>         * config/rs6000/constraints.md (wb constraint): New constraint for
>         ISA 3.0 d-form scalar addressing.
>
>         * config/rs6000/rs6000.c (mode_supports_vmx_dform): Add support
>         for ISA 3.0 D-form addressing to load SFmode/DFmode scalars into
>         Altivec registers.  Add wb constraint for Altivec registers with
>         D-form addressing.  If we have ISA 3.0 d-form support, undo
>         secondary reload support for using FPR registers if we want to do
>         D-form addressing.
>         (rs6000_debug_reg_global): Likewise.
>         (rs6000_setup_reg_addr_masks): Likewise.
>         (rs6000_init_hard_regno_mode_ok): Likewise.
>         (rs6000_secondary_reload): Likewise.
>         (rs6000_preferred_reload_class): Likewise.
>         (rs6000_secondary_reload_class): Likewise.
>
>         * config/rs6000/rs6000.h (enum r6000_reg_class_enum): Add wb
>         constraint.
>
>         * config/rs6000/rs6000.md (f32_lr2 mode attribute): Add support
>         for ISA 3.0 SFmode/DFmode d-form addressing to Altivec registers.
>         (f32_lm2): Likewise.
>         (f32_li2): Likewise.
>         (f32_sr2): Likewise.
>         (f32_sm2): Likewise.
>         (f32_si2): Likewise.
>         (f64_p9): Likewise.
>         (extendsfdf2_fpr): Likewise.
>         (mov<mode>_hardfloat): Likewise.
>         (mov<mode>_hardfloat32): Likewise.
>         (mov<mode>_hardfloat64): Likewise.
>
>         * doc/md.texi (RS/6000 constraints): Document wb constraint.
>         Fixup we constraint documentation.
>
> [gcc/testsuite]
> 2015-11-10  Michael Meissner  <meissner@linux.vnet.ibm.com>
>
>         * gcc.target/powerpc/dform-1.c: New test.
>         * gcc.target/powerpc/dform-2.c: Likewise.

This is okay.

I don't know if you want to apply it now or wait until after the
holidays in case there is any fallout.

Thanks, David