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Re: [PATCH], Add power9 support to GCC, patch #5 (ISA 3.0 fusion)
- From: Segher Boessenkool <segher at kernel dot crashing dot org>
- To: Michael Meissner <meissner at linux dot vnet dot ibm dot com>, gcc-patches at gcc dot gnu dot org, dje dot gcc at gmail dot com
- Date: Mon, 9 Nov 2015 13:57:04 -0600
- Subject: Re: [PATCH], Add power9 support to GCC, patch #5 (ISA 3.0 fusion)
- Authentication-results: sourceware.org; auth=none
- References: <20151103202911 dot GA5304 at ibm-tiger dot the-meissners dot org> <20151109004204 dot GE17170 at ibm-tiger dot the-meissners dot org> <20151109171627 dot GA13265 at gate dot crashing dot org> <20151109173419 dot GC32705 at ibm-tiger dot the-meissners dot org>
On Mon, Nov 09, 2015 at 12:34:20PM -0500, Michael Meissner wrote:
> > > +(define_insn "*toc_fusionload_<mode>"
> > > + [(set (match_operand:QHSI 0 "int_reg_operand" "=&b,??r")
> > > + (match_operand:QHSI 1 "toc_fusion_mem_wrapped" "wG,wG"))
> > > + (unspec [(const_int 0)] UNSPEC_FUSION_ADDIS)
> > > + (use (match_operand:DI 2 "base_reg_operand" "r,r"))
> > > + (clobber (match_scratch:DI 3 "=X,&b"))]
> > > + "TARGET_TOC_FUSION_INT"
> >
> > Do you need that "??r" alternative? Same for the next define_insn.
>
> Yes unfortunately. The ??r catches the case where r0 is chosen. R0 is not a
> base register, and it can't be used for power8 gpr fusion (where you use the
> value being loaded for the ADDIS instruction), but it can be used for power9
> fusion (where the ADDIS must be adjancent, but it no longer has to be the
> register being loaded).
If you have only "b", r0 will not be chosen. Does that help? Or are
you generating this pattern from somewhere else where you put in r0?
Segher