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Re: Re: [PATCH][ARM/AArch64] PR 68088: Fix RTL checking ICE due to subregs inside accumulator forwarding check


On 11/06/2015 04:46 PM, Ramana Radhakrishnan wrote:
Hi!

I faced the same issue but I had somewhat different RTL for the consumer:

     (insn 20 15 21 2 (set (reg/i:SI 0 r0)
             (minus:SI (subreg:SI (reg:DI 117) 4)
                 (mult:SI (reg:SI 123)
                     (reg:SI 114)))) gasman.c:4 48 {*mulsi3subsi})

where (reg:DI 117) is produced by umulsidi3_v6 instruction. Is it
really true that (subreg:SI (reg:DI 117) 4) may be forwarded in one
cycle in this case?
If the accumulator can be forwarded (i.e. a SImode register), there isn't a reason why a subreg:SI (reg:DI) will not get forwarded.

The subreg:SI is an artifact before register allocation, thus it's a representation issue that the patch is fixing here unless I misunderstand your question.

I mean, in my example it is not the multiplication result that is
forwarded but its upper part. So, shouldn't we check that offset in a
subreg expression is zero? Or is it ok to forward only the upper part
of a multiplication?

Thanks,
Nikolai


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