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Re: [PATCH][ARM/AArch64] PR 68088: Fix RTL checking ICE due to subregs inside accumulator forwarding check


On 10/28/2015 01:07 PM, Kyrill Tkachov wrote:
Hi all,

This RTL checking error occurs on aarch64 in aarch_accumulator_forwarding when processing an msubsi insn
with subregs:
(insn 15 14 16 3 (set (reg/v:SI 78 [ i ])
        (minus:SI (subreg:SI (reg/v:DI 76 [ aul ]) 0)
            (mult:SI (subreg:SI (reg:DI 83) 0)
(subreg:SI (reg:DI 75 [ _20 ]) 0)))) schedice.c:10 357 {*msubsi}

The register_operand predicate for that pattern allows subregs (I think correctly). The code in aarch_accumulator_forwarding doesn't take that into account and ends up
taking a REGNO of a SUBREG, causing a checking error.

This patch fixes that by stripping the subregs off the accumulator rtx before
checking that the inner expression is a REG and taking its REGNO.

The testcase now works fine with an aarch64-none-elf toolchain configure for RTL checking.

The testcase is taken verbatim from the BZ entry for PR 68088.
Since this function is shared between arm and aarch64 I've bootstrapped and tested it on both
and I'll need ok's for both ports.

Ok for trunk?

Thanks,
Kyrill

2015-10-28  Kyrylo Tkachov  <kyrylo.tkachov@arm.com>

    PR target/68088
    * config/arm/aarch-common.c (aarch_strip_subreg): New function.
    (aarch_accumulator_forwarding): Strip subregs from accumulator rtx
    when appropriate.

2015-10-28  Kyrylo Tkachov  <kyrylo.tkachov@arm.com>

    * gcc.target/aarch64/pr68088_1.c: New test.

Hi!

I faced the same issue but I had somewhat different RTL for the consumer:

    (insn 20 15 21 2 (set (reg/i:SI 0 r0)
            (minus:SI (subreg:SI (reg:DI 117) 4)
                (mult:SI (reg:SI 123)
                    (reg:SI 114)))) gasman.c:4 48 {*mulsi3subsi})

where (reg:DI 117) is produced by umulsidi3_v6 instruction. Is it
really true that (subreg:SI (reg:DI 117) 4) may be forwarded in one
cycle in this case?

Thanks,
Nikolai


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