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[PATCH][AArch64 0/8] Add D-registers to TARGET_ARRAY_MODE_SUPPORTED_P
- From: Alan Lawrence <alan dot lawrence at arm dot com>
- To: gcc-patches at gcc dot gnu dot org
- Cc: james dot greenhalgh at arm dot com, marcus dot shawcroft at arm dot com
- Date: Wed, 26 Aug 2015 14:46:51 +0100
- Subject: [PATCH][AArch64 0/8] Add D-registers to TARGET_ARRAY_MODE_SUPPORTED_P
- Authentication-results: sourceware.org; auth=none
The end goal of this series of patches is to enable 64bit vector modes for
TARGET_ARRAY_MODE_SUPPORTED_P, achieved in the last patch. At present, doing so
causes ICEs with illegal subregs (e.g. returning the middle bits from a large
int mode covering 3 vectors); the patchset avoids these by first removing EImode
(192 bits = 24 bytes = 1.5 vector registers), which is currently used for
24-byte quantities transferred to/from memory by some {ld,st}3_lane instrinsics.
There is no real need to use EImode here, it's only real purpose is that it has
size 24 bytes, so we can use BLKmode instead as long as we explicitly set the
size.
Patches 5-6 extend the same BLKmode treatment to {ld,st}{2,4}, allowing all the
expander patterns to combined in patch 7; these are not essential to the end
goal but it seemed good to be consistent. Patch 1 is a driveby, and stands in
its own right.