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Re: [PATCH] [ARM] Post-indexed addressing for NEON memory access


On Fri, Jun 19, 2015 at 7:04 PM, Charles Baylis
<charles.baylis@linaro.org> wrote:
> On 18 June 2014 at 11:06, Ramana Radhakrishnan
> <ramana.gcc@googlemail.com> wrote:
>> On Tue, Jun 17, 2014 at 4:03 PM, Charles Baylis
>> <charles.baylis@linaro.org> wrote:
>>> Your mention of larger vector modes prompted me to check that the
>>> patch has the desired result with them. In fact, the costs are
>>> estimated incorrectly which means the post_modify pattern is not used.
>>> The attached patch fixes that. (used in combination with my original
>>> patch)
>>>
>>>
>>> 2014-06-15  Charles Baylis  <charles.bayls@linaro.org>
>>>
>>>         * config/arm/arm.c (arm_new_rtx_costs): Reduce cost for mem with
>>>         embedded side effects.
>>
>> I'm not too thrilled with putting in more special cases that are not
>> table driven in there. Can you file a PR with some testcases that show
>> this so that we don't forget and CC me on it please ?
>
> I created https://gcc.gnu.org/bugzilla/show_bug.cgi?id=61551 at the time.
>
> I've come back to look at this again and would like to fix it in this
> release cycle. I still don't really understand what you mean by
> table-driven in this context. Do you still hold this view, and if so,
> could you describe what you'd like to see instead of this patch?

By table-driven I mean something similar to the existing rtx_costs
infrastructure with a walker and a data structure holding costs for
each addressing mode which are tweakable on a per-core basis.

Thus for example I'd expect this to be on a per access mode basis
along with different costs with respect to post_inc, reg indirect,
pre_inc etc. that were in a data structure and then a worker function
that peeled rtx's to obtain the appropriate cost from said
data-structure.



Ramana


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