Re: [GCC, ARM] armv8 linux toolchain asan testcase fail due to stl missing conditional code

[Kyrill Tkachov <kyrylo dot tkachov at arm dot com>]

On 03/06/15 09:32, Ramana Radhakrishnan wrote:
> > This pattern is not predicable though, i.e. it doesn't have the "predicable" attribute set to "yes".
> > Therefore the compiler should be trying to branch around here rather than try to do a cond_exec.
> > Why does the generated code above look like it's converted to conditional execution?
> > Could you produce a self-contained reduced testcase for this?
> CCFSM state machine in ARM state.
>
> arm.c (final_prescan_insn).

Ah ok.
This patch makes sense then.
As Ramana mentioned, please mark the pattern with "predicable" and also set the "predicable_short_it" attribute to "no" so that it will not be conditionalised in Thumb2 mode or when -mrestrict-it is enabled.

Thanks,
Kyrill


> Ramana
>
> > Thanks,
> > Kyrill
> >
> > > @@ -91,9 +91,9 @@
> > >       {
> > >         enum memmodel model = memmodel_from_int (INTVAL (operands[2]));
> > >         if (is_mm_relaxed (model) || is_mm_consume (model) || is_mm_acquire (model))
> > > -      return \"str<sync_sfx>\t%1, %0\";
> > > +      return \"str<sync_sfx>%?\t%1, %0\";
> > >         else
> > > -      return \"stl<sync_sfx>\t%1, %0\";
> > > +      return \"stl<sync_sfx>%?\t%1, %0\";
> > >       }
> > >     )