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[Patch ARM-AArch64/testsuite Neon intrinsics 00/20] Executable tests
- From: Christophe Lyon <christophe dot lyon at linaro dot org>
- To: gcc-patches at gcc dot gnu dot org
- Date: Wed, 27 May 2015 22:15:27 +0200
- Subject: [Patch ARM-AArch64/testsuite Neon intrinsics 00/20] Executable tests
- Authentication-results: sourceware.org; auth=none
This patch series is a follow-up to the tests I already contributed,
converted from my original testsuite.
This series consists in 20 new patches, which can be committed
independently. For vrecpe, I added the setting of the "Flush-to-Zero"
FP flag, to force AArch64 to behave the same as ARM by default.
This is the final batch, except for the vget_lane tests which I will
submit later. This should cover the subset of AdvSIMD intrinsics
common to ARMv7 and AArch64.
Tested with qemu on arm*linux, aarch64-linux.
2015-05-27 Christophe Lyon <christophe.lyon@linaro.org>
* gcc.target/aarch64/advsimd-intrinsics/arm-neon-ref.h
(_ARM_FPSCR): Add FZ field.
(clean_results): Force FZ=1 on AArch64.
* gcc.target/aarch64/advsimd-intrinsics/vrecpe.c: New file.
* gcc.target/aarch64/advsimd-intrinsics/vrecps.c: Likewise.
* gcc.target/aarch64/advsimd-intrinsics/vreinterpret.c: Likewise.
* gcc.target/aarch64/advsimd-intrinsics/vrev.c: Likewise.
* gcc.target/aarch64/advsimd-intrinsics/vrshl.c: Likewise.
* gcc.target/aarch64/advsimd-intrinsics/vrshr_n.c: Likewise.
* gcc.target/aarch64/advsimd-intrinsics/vrshrn_n.c: Likewise.
* gcc.target/aarch64/advsimd-intrinsics/vrsqrte.c: Likewise.
* gcc.target/aarch64/advsimd-intrinsics/vrsqrts.c: Likewise.
* gcc.target/aarch64/advsimd-intrinsics/vrsra_n.c: Likewise.
* gcc.target/aarch64/advsimd-intrinsics/vset_lane.c: Likewise.
* gcc.target/aarch64/advsimd-intrinsics/vshl_n.c: Likewise.
* gcc.target/aarch64/advsimd-intrinsics/vshll_n.c: Likewise.
* gcc.target/aarch64/advsimd-intrinsics/vshr_n.c: Likewise.
* gcc.target/aarch64/advsimd-intrinsics/vshrn_n.c: Likewise.
* gcc.target/aarch64/advsimd-intrinsics/vsra_n.c: Likewise.
* gcc.target/aarch64/advsimd-intrinsics/vst1_lane.c: Likewise.
* gcc.target/aarch64/advsimd-intrinsics/vstX_lane.c: Likewise.
* gcc.target/aarch64/advsimd-intrinsics/vtbX.c: Likewise.
* gcc.target/aarch64/advsimd-intrinsics/vtst.c: Likewise.
Christophe Lyon (20):
Add vrecpe tests.
Add vrecps tests.
Add vreinterpret tests.
Add vrev tests.
Add vrshl tests.
Add vshr_n tests.
Add vrshr_n tests.
Add vrshrn_n tests.
Add vrsqrte tests.
Add vrsqrts tests.
Add vrsra_n tests.
Add vset_lane tests.
Add vshll_n tests.
Add vshl_n tests.
Add vshrn_n tests.
Add vsra_n tests.
Add vst1_lane tests.
Add vstX_lane tests.
Add vtbX tests.
Add vtst tests.
.../aarch64/advsimd-intrinsics/arm-neon-ref.h | 19 +-
.../gcc.target/aarch64/advsimd-intrinsics/vrecpe.c | 154 +++++
.../gcc.target/aarch64/advsimd-intrinsics/vrecps.c | 117 ++++
.../aarch64/advsimd-intrinsics/vreinterpret.c | 741 +++++++++++++++++++++
.../gcc.target/aarch64/advsimd-intrinsics/vrev.c | 200 ++++++
.../gcc.target/aarch64/advsimd-intrinsics/vrshl.c | 627 +++++++++++++++++
.../aarch64/advsimd-intrinsics/vrshr_n.c | 504 ++++++++++++++
.../aarch64/advsimd-intrinsics/vrshrn_n.c | 143 ++++
.../aarch64/advsimd-intrinsics/vrsqrte.c | 157 +++++
.../aarch64/advsimd-intrinsics/vrsqrts.c | 118 ++++
.../aarch64/advsimd-intrinsics/vrsra_n.c | 553 +++++++++++++++
.../aarch64/advsimd-intrinsics/vset_lane.c | 99 +++
.../gcc.target/aarch64/advsimd-intrinsics/vshl_n.c | 96 +++
.../aarch64/advsimd-intrinsics/vshll_n.c | 56 ++
.../gcc.target/aarch64/advsimd-intrinsics/vshr_n.c | 95 +++
.../aarch64/advsimd-intrinsics/vshrn_n.c | 70 ++
.../gcc.target/aarch64/advsimd-intrinsics/vsra_n.c | 117 ++++
.../aarch64/advsimd-intrinsics/vst1_lane.c | 93 +++
.../aarch64/advsimd-intrinsics/vstX_lane.c | 578 ++++++++++++++++
.../gcc.target/aarch64/advsimd-intrinsics/vtbX.c | 289 ++++++++
.../gcc.target/aarch64/advsimd-intrinsics/vtst.c | 120 ++++
21 files changed, 4940 insertions(+), 6 deletions(-)
create mode 100644 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vrecpe.c
create mode 100644 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vrecps.c
create mode 100644 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vreinterpret.c
create mode 100644 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vrev.c
create mode 100644 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vrshl.c
create mode 100644 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vrshr_n.c
create mode 100644 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vrshrn_n.c
create mode 100644 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vrsqrte.c
create mode 100644 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vrsqrts.c
create mode 100644 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vrsra_n.c
create mode 100644 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vset_lane.c
create mode 100644 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vshl_n.c
create mode 100644 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vshll_n.c
create mode 100644 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vshr_n.c
create mode 100644 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vshrn_n.c
create mode 100644 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vsra_n.c
create mode 100644 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst1_lane.c
create mode 100644 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vstX_lane.c
create mode 100644 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vtbX.c
create mode 100644 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vtst.c
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2.1.4