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Re: [PING^2] [PATCH] [AArch64, NEON] Improve vmulX intrinsics


Hi Jiangjiji,

This is definitely stage 1 material by now...
At my glance it all looks like the right approach, I have a question below:

On 12/03/15 09:20, Jiangjiji wrote:
+
+(define_insn "aarch64_fmulx_lane<mode>"
+  [(set (match_operand:VDQF 0 "register_operand" "=w")
+        (unspec:VDQF  [(match_operand:VDQF 1 "register_operand" "w")
+                       (match_operand:<VDQF_Q> 2 "register_operand" "w")
+                       (match_operand:SI 3 "immediate_operand" "i")]
+                      UNSPEC_FMULX_LANE))]
+ "TARGET_SIMD"
+ "fmulx\\t%0.<vtype>, %1.<vtype>, %2.<vetype>"
+  [(set_attr "type" "neon_mul_s")]
+)
Where did operand 3 go? Shouldn't his be the lane-element variant of fmulx?

Thanks,
Kyrill


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