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Re: [PATCH][AArch64] Improve bit-test-branch pattern to avoid unnecessary register clobber


On Mon, Jan 19, 2015 at 10:28:47AM +0000, Jiong Wang wrote:
> On 14/01/15 22:59, Richard Henderson wrote:
> >On 12/15/2014 07:36 AM, Jiong Wang wrote:
> >>+	char buf[64];
> >>+	uint64_t val = ((uint64_t) 1) << UINTVAL (operands[1]);
> >>+	sprintf (buf, "tst\t%%<w>0, %"PRId64, val);
> >>+	output_asm_insn (buf, operands);
> >>+	return "<bcond>\t%l2";
> >Better to simply modify the operand, as in
> >
> >   operands[1] = GEN_INT (HOST_WIDE_INT_1U << UINTVAL (operands[1]));
> >   return "tst\t%<w>0, %1\;<bcond>\t%l2";
> 
> thanks, fixed.
> 
> ok for trunk ?
> 
> gcc/
> 
> 2015-01-19 Ramana Radhakrishnanramana.radhakrishnan@arm.com
>            Jiong Wangjiong.wang@arm.com

That is not the right name/email format for ChangeLog entries.

> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/aarch64/long_range_bit_test_branch_1.c

What is aarch64 specific on the testcase?  Best would be to turn into into
an executable testcase (add __attribute__((noinline, noclone)) to dec and
define somehow, perhaps with asm volatile with "memory" clobber in it)
to check that it also works fine at runtime, but even if you don't, putting
it into gcc.c-torture/compile/ might be preferrable over putting it into
aarch64 specific dir.

	Jakub


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