[PATCH 1/3][AArch64]Replace __builtin_aarch64_createv1df with a cast, cleanup

[Alan Lawrence <alan dot lawrence at arm dot com>]

Now that float64x1_t is a vector, casting to it from a unit64_t causes the bit 
pattern to be reinterpreted, just as vcreate_f64 should. (Previously when 
float64x1_t was still a scalar, casting caused a conversion.) Hence, replace the 
__builtin with a cast. None of the other variants of the aarch64_create pattern 
were used, so remove it, and associated guff.

Also have to inhibit optimization of some testcases, as the midend can see 
through casts, whereas it couldn't see builtins ;).

The affected intrinsics are all covered by tests gcc.target/aarch64/vrnd_f64_1, 
vreinterpret_f64_1.c, vget_high_1.c.

gcc/ChangeLog:

	* config/aarch64/aarch64-builtins.c (TYPES_CREATE): Remove.
	* config/aarch64/aarch64-simd-builtins.def (create): Remove.
	* config/aarch64/aarch64-simd.md (aarch64_create<mode>): Remove.
	* config/aarch64/arm_neon.h (vcreate_f64, vreinterpret_f64_s64,
	vreinterpret_f64_u64): Replace __builtin_aarch64_createv1df with C casts.
	* config/aarch64/iterators.md (VD1): Remove.

gcc/testsuite/ChangeLog:

	* gcc.target/aarch64/simd/vfma_f64.c: Add asm volatile memory.
	* gcc.target/aarch64/simd/vfms_f64.c: Likewise.

diff --git a/gcc/config/aarch64/aarch64-builtins.c b/gcc/config/aarch64/aarch64-builtins.c
index 527445c5c7788bc37f41d9c3428f59a18410a93a..c130f80b869304087205e21aa644d76c06749309 100644
--- a/gcc/config/aarch64/aarch64-builtins.c
+++ b/gcc/config/aarch64/aarch64-builtins.c
@@ -136,7 +136,6 @@ static enum aarch64_type_qualifiers
 aarch64_types_unopu_qualifiers[SIMD_MAX_BUILTIN_ARGS]
   = { qualifier_unsigned, qualifier_unsigned };
 #define TYPES_UNOPU (aarch64_types_unopu_qualifiers)
-#define TYPES_CREATE (aarch64_types_unop_qualifiers)
 static enum aarch64_type_qualifiers
 aarch64_types_binop_qualifiers[SIMD_MAX_BUILTIN_ARGS]
   = { qualifier_none, qualifier_none, qualifier_maybe_immediate };
diff --git a/gcc/config/aarch64/aarch64-simd-builtins.def b/gcc/config/aarch64/aarch64-simd-builtins.def
index 62b7f3357d12f2a4a483588e3ccf027c3f957c20..8cdb9609520a227f33008efa9201d7771e241755 100644
--- a/gcc/config/aarch64/aarch64-simd-builtins.def
+++ b/gcc/config/aarch64/aarch64-simd-builtins.def
@@ -39,7 +39,6 @@
    1-9 - CODE_FOR_<name><mode><1-9>
    10 - CODE_FOR_<name><mode>.  */
 
-  BUILTIN_VD1 (CREATE, create, 0)
   BUILTIN_VDC (COMBINE, combine, 0)
   BUILTIN_VB (BINOP, pmul, 0)
   BUILTIN_VDQF (UNOP, sqrt, 2)
diff --git a/gcc/config/aarch64/aarch64-simd.md b/gcc/config/aarch64/aarch64-simd.md
index ef196e4b6fb39c0d2fd9ebfee76abab8369b1e92..00b59d3a352325e77632daa9723f3df4850cf922 100644
--- a/gcc/config/aarch64/aarch64-simd.md
+++ b/gcc/config/aarch64/aarch64-simd.md
@@ -2315,16 +2315,6 @@
 
 ;; Patterns for AArch64 SIMD Intrinsics.
 
-(define_expand "aarch64_create<mode>"
-  [(match_operand:VD1 0 "register_operand" "")
-   (match_operand:DI 1 "general_operand" "")]
-  "TARGET_SIMD"
-{
-  rtx src = gen_lowpart (<MODE>mode, operands[1]);
-  emit_move_insn (operands[0], src);
-  DONE;
-})
-
 ;; Lane extraction with sign extension to general purpose register.
 (define_insn "*aarch64_get_lane_extend<GPI:mode><VDQQH:mode>"
   [(set (match_operand:GPI 0 "register_operand" "=r")
diff --git a/gcc/config/aarch64/arm_neon.h b/gcc/config/aarch64/arm_neon.h
index 0ec1a24a52d81a6f8a2d45c0a931e771972d5eef..4a0d718642f8a3cb56281a70435b1b6445ee35be 100644
--- a/gcc/config/aarch64/arm_neon.h
+++ b/gcc/config/aarch64/arm_neon.h
@@ -2662,7 +2662,7 @@ vcreate_u64 (uint64_t __a)
 __extension__ static __inline float64x1_t __attribute__ ((__always_inline__))
 vcreate_f64 (uint64_t __a)
 {
-  return __builtin_aarch64_createv1df (__a);
+  return (float64x1_t) __a;
 }
 
 __extension__ static __inline poly8x8_t __attribute__ ((__always_inline__))
@@ -3262,7 +3262,7 @@ vreinterpret_f64_s32 (int32x2_t __a)
 __extension__ static __inline float64x1_t __attribute__((__always_inline__))
 vreinterpret_f64_s64 (int64x1_t __a)
 {
-  return __builtin_aarch64_createv1df ((uint64_t) vget_lane_s64 (__a, 0));
+  return (float64x1_t) __a;
 }
 
 __extension__ static __inline float64x1_t __attribute__((__always_inline__))
@@ -3286,7 +3286,7 @@ vreinterpret_f64_u32 (uint32x2_t __a)
 __extension__ static __inline float64x1_t __attribute__((__always_inline__))
 vreinterpret_f64_u64 (uint64x1_t __a)
 {
-  return __builtin_aarch64_createv1df (vget_lane_u64 (__a, 0));
+  return (float64x1_t) __a;
 }
 
 __extension__ static __inline float64x2_t __attribute__((__always_inline__))
diff --git a/gcc/config/aarch64/iterators.md b/gcc/config/aarch64/iterators.md
index 74c71fcc8047f221f28cedaba8fca80995576cc7..c5abc3af79405fa4cd5ab2fd6f9e756b5907a3ae 100644
--- a/gcc/config/aarch64/iterators.md
+++ b/gcc/config/aarch64/iterators.md
@@ -147,9 +147,6 @@
 ;; Double vector modes for combines.
 (define_mode_iterator VDIC [V8QI V4HI V2SI])
 
-;; Double vector modes inc V1DF
-(define_mode_iterator VD1 [V8QI V4HI V2SI V2SF V1DF])
-
 ;; Vector modes except double int.
 (define_mode_iterator VDQIF [V8QI V16QI V4HI V8HI V2SI V4SI V2SF V4SF V2DF])
 
diff --git a/gcc/testsuite/gcc.target/aarch64/simd/vfma_f64.c b/gcc/testsuite/gcc.target/aarch64/simd/vfma_f64.c
index 272b79ceb395a8f44d76ea1ac833a9cd64210711..8083d2c0d68cd9da07ff8235f6cd5c7549d0571a 100644
--- a/gcc/testsuite/gcc.target/aarch64/simd/vfma_f64.c
+++ b/gcc/testsuite/gcc.target/aarch64/simd/vfma_f64.c
@@ -7,6 +7,10 @@
 
 #define EPS 1.0e-15
 
+#define INHIB_OPT(x) asm volatile ("mov %d0, %1.d[0]"	\
+				   : "=w"(x)		\
+				   : "w"(x)		\
+				   : /* No clobbers. */);
 
 extern void abort (void);
 
@@ -24,6 +28,10 @@ main (void)
   arg2 = vcreate_f64 (0x3fa88480812d6670ULL);
   arg3 = vcreate_f64 (0x3fd5791ae2a92572ULL);
 
+  INHIB_OPT (arg1);
+  INHIB_OPT (arg2);
+  INHIB_OPT (arg3);
+
   expected = 0.6280448184360076;
   actual = vget_lane_f64 (vfma_f64 (arg1, arg2, arg3), 0);
 
diff --git a/gcc/testsuite/gcc.target/aarch64/simd/vfms_f64.c b/gcc/testsuite/gcc.target/aarch64/simd/vfms_f64.c
index f6e1f77886dd3af7374305a45b0055e9b2e3997d..ede140d75386faf91a038f3b59b7686d0a568ab2 100644
--- a/gcc/testsuite/gcc.target/aarch64/simd/vfms_f64.c
+++ b/gcc/testsuite/gcc.target/aarch64/simd/vfms_f64.c
@@ -7,6 +7,10 @@
 
 #define EPS 1.0e-15
 
+#define INHIB_OPT(x) asm volatile ("mov %d0, %1.d[0]"   \
+                                   : "=w"(x)           \
+                                   : "w"(x)            \
+                                   : /* No clobbers. */);
 
 extern void abort (void);
 
@@ -24,6 +28,10 @@ main (void)
   arg2 = vcreate_f64 (0x3fe6b78680fa29ceULL);
   arg3 = vcreate_f64 (0x3feea3cbf921fbe0ULL);
 
+  INHIB_OPT (arg1);
+  INHIB_OPT (arg2);
+  INHIB_OPT (arg3);
+
   expected = 4.4964705746355915e-2;
   actual = vget_lane_f64 (vfms_f64 (arg1, arg2, arg3), 0);