Re: PATCH [3 of 7], rs6000, add support for scalar floating point in Altivec registers

[David Edelsohn <dje dot gcc at gmail dot com>]

On Tue, Nov 11, 2014 at 8:02 PM, Michael Meissner
<meissner@linux.vnet.ibm.com> wrote:
> Last year, in preparation for the upper regs patch, I went through the
> instructions, and changed the iterators, so the vector support was in vsx.md,
> while the scalar support was in rs6000.md.  I missed the int<->fp conversion
> operators.  This patch moves the scalar support into rs6000.md.  Note, this
> patch will generate the non-VSX form of the conversion instrution if the
> registers are both traditional floating point (in GCC 4.x, it would generate
> the VSX scalar operation).  The upper register support will not be enabled
> until a future patch.  Is this patch acceptable to be checked in when the
> PowerPC bootstraps?
>
> I also fixed up the tests that were affected by these changes.
>
> [gcc, patch]
> 2014-11-11  Michael Meissner  <meissner@linux.vnet.ibm.com>
>
>         * config/rs6000/vsx.md (vsx_float<VSi><mode>2): Only provide the
>         vector forms of the instructions.  Move VSX scalar forms to
>         rs6000.md, and add support for -mupper-regs-sf.
>         (vsx_floatuns<VSi><mode>2): Likewise.
>         (vsx_fix_trunc<mode><VSi>2): Likewise.
>         (vsx_fixuns_trunc<mode><VSi>2): Likewise.
>         (vsx_float_fix_<mode>2): Delete DF version, rename to
>         vsx_float_fix_v2df2.
>         (vsx_float_fix_v2df2): Likewise.
>
>         * config/rs6000/rs6000.md (Fa): New mode attribute to give
>         constraint for the Altivec registers for a type.
>         (extendsfdf2_fpr): Use correct constraint.
>         (copysign<mode>3_fcpsgn): For SFmode, use correct xscpsgndp
>         instruction.
>         (floatsi<mode>2_lfiwax): Add support for -mupper-regs-{sf,df}.
>         Generate the non-VSX instruction if all registers were FPRs.  Do
>         not use the patterns in vsx.md for scalar operations.
>         (floatsi<mode>2_lfiwax_mem): Likewise.
>         (floatunssi<mode>2_lfiwzx): Likewise.
>         (floatunssi<mode>2_lfiwzx_mem): Likewise.
>         (fix_trunc<mode>di2_fctidz): Likewise.
>         (fixuns_trunc<mode>di2_fctiduz): Likewise.
>         (fctiwz_<mode>): Likewise.
>         (fctiwuz_<mode>): Likewise.
>         (friz): Likewise.
>         (floatdidf2_fpr): Likewise.
>         (floatdidf2_mem): Likewise.
>         (floatunsdidf2): Likewise.
>         (floatunsdidf2_fcfidu): Likewise.
>         (floatunsdidf2_mem): Likewise.
>         (floatdisf2_fcfids): Likewise.
>         (floatdisf2_mem): Likewise.
>         (floatdisf2_internal1): Add explicit test for not FCFIDS to make
>         it more obvious that the code is for pre-ISA 2.06 machines.
>         (floatdisf2_internal2): Likewise.
>         (floatunsdisf2_fcfidus): Add support for -mupper-regs-{sf,df}.
>         Generate the non-VSX instruction if all registers were FPRs.  Do
>         not use the patterns in vsx.md for scalar operations.
>         (floatunsdisf2_mem): Likewise.
>
> [gcc/testsuite]
> 2014-11-11  Michael Meissner  <meissner@linux.vnet.ibm.com>
>
>         * gcc.target/powerpc/ppc-fpconv-1.c: Adjust for -mupper-regs-df
>         changes.
>         * gcc.target/powerpc/ppc-fpconv-2.c: Likewise.
>         * gcc.target/powerpc/ppc-fpconv-3.c: Likewise.
>         * gcc.target/powerpc/ppc-fpconv-4.c: Likewise.
>         * gcc.target/powerpc/ppc-fpconv-5.c: Likewise.
>         * gcc.target/powerpc/ppc-fpconv-6.c: Likewise.
>         * gcc.target/powerpc/ppc-fpconv-7.c: Likewise.
>         * gcc.target/powerpc/ppc-fpconv-8.c: Likewise.
>         * gcc.target/powerpc/ppc-fpconv-9.c: Likewise.
>         * gcc.target/powerpc/ppc-fpconv-10.c: Likewise.
>         * gcc.target/powerpc/ppc-round.c: Likewise.

Okay.

Thanks, David