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Re: [Patch] Add MIPS flag to avoid use of ldc1/sdc1/ldxc1/sdxc1
- From: Ramana Radhakrishnan <ramana dot gcc at googlemail dot com>
- To: Matthew Fortune <Matthew dot Fortune at imgtec dot com>
- Cc: Andrew Pinski <pinskia at gmail dot com>, "Moore, Catherine" <Catherine_Moore at mentor dot com>, Steve Ellcey <Steve dot Ellcey at imgtec dot com>, GCC Patches <gcc-patches at gcc dot gnu dot org>
- Date: Tue, 28 Oct 2014 12:28:23 +0000
- Subject: Re: [Patch] Add MIPS flag to avoid use of ldc1/sdc1/ldxc1/sdxc1
- Authentication-results: sourceware.org; auth=none
- References: <4f0faaab-5dd4-40c8-b66d-feb9bb515c0d at BAMAIL02 dot ba dot imgtec dot org> <CA+=Sn1=STsjh2pms1Sp=a05jji=ck9hYJKYjGH3KM9GDmC+vhg at mail dot gmail dot com> <FD3DCEAC5B03E9408544A1E416F11242016E7592D0 at NA-MBX-04 dot mgc dot mentorg dot com> <CA+=Sn1=wpxqyw_prTs-v_yZ47yhrRqWs_CobvgtCcrEKT4VJXA at mail dot gmail dot com> <FD3DCEAC5B03E9408544A1E416F11242016E75930A at NA-MBX-04 dot mgc dot mentorg dot com> <CA+=Sn1nYbc=3ZqV6g_4q27cug_z9759vFFVHk9zBg4OSj9bntQ at mail dot gmail dot com> <6D39441BF12EF246A7ABCE6654B0235320F344E8 at LEMAIL01 dot le dot imgtec dot org>
- Reply-to: ramrad01 at arm dot com
On Tue, Oct 28, 2014 at 11:46 AM, Matthew Fortune
<Matthew.Fortune@imgtec.com> wrote:
>> >> > Do you have an objection to allowing an option to disable these
>> >> instructions (despite the reason for wanting to do so)?
>> >>
>> >> Yes this seems like a bad workaround for broken code.
>> >>
>> > Well, we work around broken hardware all the time. What would you
>> suggest that Steve do instead?
>>
>> We work around broken hardware all the time yes but that is something
>> which is hard to change. Software is easier to fix. That does not
>> mean in the compiler. The compiler team should not get themselves in
>> the business of working around broken software that depends on
>> undefined behavior (this undefined behavior is very obvious and easier
>> to fix in the source of the problem). Report the bug to Google.
>
> I'm mostly in agreement with Andrew on this. I'd like to understand more
> about the use-case and what happens for other architectures (only ARM
> and x86 are really relevant here I guess). I believe x86 will just
> happily load/store doubles to 4-byte aligned addresses but I'm not sure
> for ARM. If ARM has to take unaligned access faults for this then I
> think MIPS simply has to do the same.
On AArch32 (ARM) the equivalent general purpose instructions (ldrd /
strd , vldr / vstr, vpush / vpop, vldm / vstm) require only 4 byte
alignment in the architecture. The only case where we may have a
problem is with ldrexd / strexd instructions which are used for
atomics but I'm not sure if that is under question / discussion here.
This is really an application "design / portability" issue rather than
anything else. So, there's no need to take alignment faults on AArch32
in this situation. Oh and before someone asks AArch64 is not a strict
alignment target and so the compiler is free to emit unaligned
accesses unless it is told not to do so.
regards
Ramana