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Re: [PATCH i386 AVX512] [63.1/n] Add vpshufb, perm autogen (except for v64qi).


> > 
> > The patch is OK with the above improvement.
> > 
> >
> 
> Will commit version below, if no objections in 24 hours.
> 
>
Sorry,
I've missed palignr, which should also have v64qi version,
and lost return in expand_vec_perm_palignr case
(this caused avx512f-vec-unpack test failures).
Patch below fixes it. Ok for trunk?

2014-10-20  Ilya Tocar  <ilya.tocar@intel.com>

	* config/i386/i386.c (expand_vec_perm_1): Fix
	expand_vec_perm_palignr case.
	* config/i386/sse.md (<ssse3_avx2>_palignr<mode>_mask): Use
	VI1_AVX512.

---
 gcc/config/i386/i386.c |  1 +
 gcc/config/i386/sse.md | 12 ++++++------
 2 files changed, 7 insertions(+), 6 deletions(-)

diff --git a/gcc/config/i386/i386.c b/gcc/config/i386/i386.c
index 33b21f4..34273ca 100644
--- a/gcc/config/i386/i386.c
+++ b/gcc/config/i386/i386.c
@@ -43552,6 +43552,7 @@ expand_vec_perm_1 (struct expand_vec_perm_d *d)
 
   /* Try the AVX2 vpalignr instruction.  */
   if (expand_vec_perm_palignr (d, true))
+    return true;
 
   /* Try the AVX512F vpermi2 instructions.  */
   if (ix86_expand_vec_perm_vpermi2 (NULL_RTX, NULL_RTX, NULL_RTX, NULL_RTX, d))
diff --git a/gcc/config/i386/sse.md b/gcc/config/i386/sse.md
index 8157045..a3f336f 100644
--- a/gcc/config/i386/sse.md
+++ b/gcc/config/i386/sse.md
@@ -13716,14 +13716,14 @@
    (set_attr "mode" "DI")])
 
 (define_insn "<ssse3_avx2>_palignr<mode>_mask"
-  [(set (match_operand:VI1_AVX2 0 "register_operand" "=v")
-        (vec_merge:VI1_AVX2
-	  (unspec:VI1_AVX2
-	    [(match_operand:VI1_AVX2 1 "register_operand" "v")
-	     (match_operand:VI1_AVX2 2 "nonimmediate_operand" "vm")
+  [(set (match_operand:VI1_AVX512 0 "register_operand" "=v")
+        (vec_merge:VI1_AVX512
+	  (unspec:VI1_AVX512
+	    [(match_operand:VI1_AVX512 1 "register_operand" "v")
+	     (match_operand:VI1_AVX512 2 "nonimmediate_operand" "vm")
 	     (match_operand:SI 3 "const_0_to_255_mul_8_operand" "n")]
 	    UNSPEC_PALIGNR)
-	(match_operand:VI1_AVX2 4 "vector_move_operand" "0C")
+	(match_operand:VI1_AVX512 4 "vector_move_operand" "0C")
 	(match_operand:<avx512fmaskmode> 5 "register_operand" "Yk")))]
   "TARGET_AVX512BW && (<MODE_SIZE> == 64 || TARGET_AVX512VL)"
 {
-- 
1.8.3.1


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