This is the mail archive of the gcc-patches@gcc.gnu.org mailing list for the GCC project.


Index Nav: [Date Index] [Subject Index] [Author Index] [Thread Index]
Message Nav: [Date Prev] [Date Next] [Thread Prev] [Thread Next]
Other format: [Raw text]

Re: [PATCH] Fix typo in comment for IRA


Hi Marc:
>> -     -1 if it is not a cost classe.  */
>> +     -1 if it is not a cost classes.  */
>
> "a cost class", no plural here.

Thank you for correcting me :)


Hi Jeff:

Thanks, and updated patch in attachment,

However I don't have commit right yet, can you help me to commit it? thanks.
From e00ad515d77fd491266b743548f3c0705731fb71 Mon Sep 17 00:00:00 2001
From: Kito Cheng <kito@andestech.com>
Date: Fri, 22 Aug 2014 16:27:18 +0800
Subject: [PATCH] Fix typo in comment for IRA

2014-10-14  Kito Cheng  <kito@0xlab.org>

	* ira.c: Fix typo in comment.
	* ira.h: Ditto.
	* ira-build.c: Ditto.
	* ira-color.c: Ditto.
	* ira-emit.c: Ditto.
	* ira-int.h: Ditto.
	* ira-lives.c: Ditto.
---
 gcc/ira-build.c |  2 +-
 gcc/ira-color.c | 10 +++++-----
 gcc/ira-costs.c |  8 ++++----
 gcc/ira-emit.c  |  4 ++--
 gcc/ira-int.h   |  4 ++--
 gcc/ira-lives.c |  2 +-
 gcc/ira.c       | 24 ++++++++++++------------
 gcc/ira.h       |  2 +-
 8 files changed, 28 insertions(+), 28 deletions(-)

diff --git a/gcc/ira-build.c b/gcc/ira-build.c
index 9c99166..98df8cd 100644
--- a/gcc/ira-build.c
+++ b/gcc/ira-build.c
@@ -1224,7 +1224,7 @@ ira_create_pref (ira_allocno_t a, int hard_regno, int freq)
   return pref;
 }
 
-/* Attach a pref PREF to the cooresponding allocno.  */
+/* Attach a pref PREF to the corresponding allocno.  */
 static void
 add_allocno_pref_to_list (ira_pref_t pref)
 {
diff --git a/gcc/ira-color.c b/gcc/ira-color.c
index dffe40a..c8e8f9a 100644
--- a/gcc/ira-color.c
+++ b/gcc/ira-color.c
@@ -104,7 +104,7 @@ struct update_cost_record
 struct allocno_color_data
 {
   /* TRUE value means that the allocno was not removed yet from the
-     conflicting graph during colouring.  */
+     conflicting graph during coloring.  */
   unsigned int in_graph_p : 1;
   /* TRUE if it is put on the stack to make other allocnos
      colorable.  */
@@ -1203,7 +1203,7 @@ struct update_cost_queue_elem
      connecting this allocno to the one being allocated.  */
   int divisor;
 
-  /* Allocno from which we are chaning costs of connected allocnos.
+  /* Allocno from which we are chaining costs of connected allocnos.
      It is used not go back in graph of allocnos connected by
      copies.  */
   ira_allocno_t from;
@@ -1928,7 +1928,7 @@ copy_freq_compare_func (const void *v1p, const void *v2p)
   if (pri2 - pri1)
     return pri2 - pri1;
 
-  /* If freqencies are equal, sort by copies, so that the results of
+  /* If frequencies are equal, sort by copies, so that the results of
      qsort leave nothing to chance.  */
   return cp1->num - cp2->num;
 }
@@ -1983,7 +1983,7 @@ merge_threads (ira_allocno_t t1, ira_allocno_t t2)
   ALLOCNO_COLOR_DATA (t1)->thread_freq += ALLOCNO_COLOR_DATA (t2)->thread_freq;
 }
 
-/* Create threads by processing CP_NUM copies from sorted)ciopeis.  We
+/* Create threads by processing CP_NUM copies from sorted copies.  We
    process the most expensive copies first.  */
 static void
 form_threads_from_copies (int cp_num)
@@ -3608,7 +3608,7 @@ conflict_by_live_ranges_p (int regno1, int regno2)
 
   ira_assert (regno1 >= FIRST_PSEUDO_REGISTER
 	      && regno2 >= FIRST_PSEUDO_REGISTER);
-  /* Reg info caclulated by dataflow infrastructure can be different
+  /* Reg info calculated by dataflow infrastructure can be different
      from one calculated by regclass.  */
   if ((a1 = ira_loop_tree_root->regno_allocno_map[regno1]) == NULL
       || (a2 = ira_loop_tree_root->regno_allocno_map[regno2]) == NULL)
diff --git a/gcc/ira-costs.c b/gcc/ira-costs.c
index 1edadec..775d4aa 100644
--- a/gcc/ira-costs.c
+++ b/gcc/ira-costs.c
@@ -118,7 +118,7 @@ struct cost_classes
   /* Container of the cost classes.  */
   enum reg_class classes[N_REG_CLASSES];
   /* Map reg class -> index of the reg class in the previous array.
-     -1 if it is not a cost classe.  */
+     -1 if it is not a cost class.  */
   int index[N_REG_CLASSES];
   /* Map hard regno index of first class in array CLASSES containing
      the hard regno, -1 otherwise.  */
@@ -277,7 +277,7 @@ setup_regno_cost_classes_by_aclass (int regno, enum reg_class aclass)
    decrease number of cost classes for the pseudo, if hard registers
    of some important classes can not hold a value of MODE.  So the
    pseudo can not get hard register of some important classes and cost
-   calculation for such important classes is only waisting CPU
+   calculation for such important classes is only wasting CPU
    time.  */
 static void
 setup_regno_cost_classes_by_mode (int regno, enum machine_mode mode)
@@ -314,7 +314,7 @@ setup_regno_cost_classes_by_mode (int regno, enum machine_mode mode)
   regno_cost_classes[regno] = classes_ptr;
 }
 
-/* Finilize info about the cost classes for each pseudo.  */
+/* Finalize info about the cost classes for each pseudo.  */
 static void
 finish_regno_cost_classes (void)
 {
@@ -1243,7 +1243,7 @@ record_operand_costs (rtx_insn *insn, enum reg_class *pref)
      then we may want to adjust the cost of that register class to -1.
 
      Avoid the adjustment if the source does not die to avoid
-     stressing of register allocator by preferrencing two colliding
+     stressing of register allocator by preferencing two colliding
      registers into single class.
 
      Also avoid the adjustment if a copy between hard registers of the
diff --git a/gcc/ira-emit.c b/gcc/ira-emit.c
index 676ee1a..5361234 100644
--- a/gcc/ira-emit.c
+++ b/gcc/ira-emit.c
@@ -777,7 +777,7 @@ modify_move_list (move_t list)
 
   if (list == NULL)
     return NULL;
-  /* Creat move deps.  */
+  /* Create move deps.  */
   curr_tick++;
   for (move = list; move != NULL; move = move->next)
     {
@@ -812,7 +812,7 @@ modify_move_list (move_t list)
 	  move->deps_num = n;
 	}
     }
-  /* Toplogical sorting:  */
+  /* Topological sorting:  */
   move_vec.truncate (0);
   for (move = list; move != NULL; move = move->next)
     traverse_moves (move);
diff --git a/gcc/ira-int.h b/gcc/ira-int.h
index c5b273a..ec42638 100644
--- a/gcc/ira-int.h
+++ b/gcc/ira-int.h
@@ -531,7 +531,7 @@ extern ira_object_t *ira_object_id_map;
 /* The size of the previous array.  */
 extern int ira_objects_num;
 
-/* The following structure represents a hard register prefererence of
+/* The following structure represents a hard register preference of
    allocno.  The preference represent move insns or potential move
    insns usually because of two operand insn constraints.  One move
    operand is a hard register.  */
@@ -546,7 +546,7 @@ struct ira_allocno_pref
   int freq;
   /* Given allocno.  */
   ira_allocno_t allocno;
-  /* All prefernces with the same allocno are linked by the following
+  /* All preferences with the same allocno are linked by the following
      member.  */
   ira_pref_t next_pref;
 };
diff --git a/gcc/ira-lives.c b/gcc/ira-lives.c
index bb6f235..1d41053 100644
--- a/gcc/ira-lives.c
+++ b/gcc/ira-lives.c
@@ -1227,7 +1227,7 @@ process_bb_node_lives (ira_loop_tree_node_t loop_tree_node)
 		  sparseset_set_bit (allocnos_processed, num);
 
 		  if (allocno_saved_at_call[num] != last_call_num)
-		    /* Here we are mimicking caller-save.c behaviour
+		    /* Here we are mimicking caller-save.c behavior
 		       which does not save hard register at a call if
 		       it was saved on previous call in the same basic
 		       block and the hard register was not mentioned
diff --git a/gcc/ira.c b/gcc/ira.c
index ebd2c21..aac1fad 100644
--- a/gcc/ira.c
+++ b/gcc/ira.c
@@ -153,7 +153,7 @@ along with GCC; see the file COPYING3.  If not see
          calculates its initial (non-accumulated) cost of memory and
          each hard-register of its allocno class (file ira-cost.c).
 
-       * IRA creates live ranges of each allocno, calulates register
+       * IRA creates live ranges of each allocno, calculates register
          pressure for each pressure class in each region, sets up
          conflict hard registers for each allocno and info about calls
          the allocno lives through (file ira-lives.c).
@@ -245,7 +245,7 @@ along with GCC; see the file COPYING3.  If not see
          hard-register for allocnos conflicting with given allocno.
 
        * Chaitin-Briggs coloring assigns as many pseudos as possible
-         to hard registers.  After coloringh we try to improve
+         to hard registers.  After coloring we try to improve
          allocation with cost point of view.  We improve the
          allocation by spilling some allocnos and assigning the freed
          hard registers to other allocnos if it decreases the overall
@@ -307,7 +307,7 @@ along with GCC; see the file COPYING3.  If not see
        rebuilding would be, but is much faster.
 
      o After IR flattening, IRA tries to assign hard registers to all
-       spilled allocnos.  This is impelemented by a simple and fast
+       spilled allocnos.  This is implemented by a simple and fast
        priority coloring algorithm (see function
        ira_reassign_conflict_allocnos::ira-color.c).  Here new allocnos
        created during the code change pass can be assigned to hard
@@ -328,7 +328,7 @@ along with GCC; see the file COPYING3.  If not see
          in places where the pseudo-register lives.
 
    IRA uses a lot of data representing the target processors.  These
-   data are initilized in file ira.c.
+   data are initialized in file ira.c.
 
    If function has no loops (or the loops are ignored when
    -fira-algorithm=CB is used), we have classic Chaitin-Briggs
@@ -898,7 +898,7 @@ setup_pressure_classes (void)
 	  IOR_HARD_REG_SET (temp_hard_regset, reg_class_contents[cl]);
       }
     for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
-      /* Some targets (like SPARC with ICC reg) have alocatable regs
+      /* Some targets (like SPARC with ICC reg) have allocatable regs
 	 for which no reg class is defined.  */
       if (REGNO_REG_CLASS (i) == NO_REGS)
 	SET_HARD_REG_BIT (ignore_hard_regs, i);
@@ -959,7 +959,7 @@ setup_uniform_class_p (void)
 /* Set up IRA_ALLOCNO_CLASSES, IRA_ALLOCNO_CLASSES_NUM,
    IRA_IMPORTANT_CLASSES, and IRA_IMPORTANT_CLASSES_NUM.
 
-   Target may have many subtargets and not all target hard regiters can
+   Target may have many subtargets and not all target hard registers can
    be used for allocation, e.g. x86 port in 32-bit mode can not use
    hard registers introduced in x86-64 like r8-r15).  Some classes
    might have the same allocatable hard registers, e.g.  INDEX_REGS
@@ -1019,7 +1019,7 @@ setup_allocno_and_important_classes (void)
   classes[n] = LIM_REG_CLASSES;
 
   /* Set up classes which can be used for allocnos as classes
-     conatining non-empty unique sets of allocatable hard
+     containing non-empty unique sets of allocatable hard
      registers.  */
   ira_allocno_classes_num = 0;
   for (i = 0; (cl = classes[i]) != LIM_REG_CLASSES; i++)
@@ -1313,7 +1313,7 @@ setup_reg_class_relations (void)
 	      if (important_class_p[cl3]
 		  && hard_reg_set_subset_p (temp_hard_regset, union_set))
 		{
-		  /* CL3 allocatbale hard register set is inside of
+		  /* CL3 allocatable hard register set is inside of
 		     union of allocatable hard register sets of CL1
 		     and CL2.  */
 		  COPY_HARD_REG_SET
@@ -1366,7 +1366,7 @@ setup_reg_class_relations (void)
     }
 }
 
-/* Output all unifrom and important classes into file F.  */
+/* Output all uniform and important classes into file F.  */
 static void
 print_unform_and_important_classes (FILE *f)
 {
@@ -2774,7 +2774,7 @@ setup_preferred_alternate_classes_for_new_pseudos (int start)
 }
 
 
-/* The number of entries allocated in teg_info.  */
+/* The number of entries allocated in reg_info.  */
 static int allocated_reg_info_size;
 
 /* Regional allocation can create new pseudo-registers.  This function
@@ -3349,7 +3349,7 @@ update_equiv_regs (void)
   init_alias_analysis ();
 
   /* Scan insns and set pdx_subregs[regno] if the reg is used in a
-     paradoxical subreg. Don't set such reg sequivalent to a mem,
+     paradoxical subreg. Don't set such reg equivalent to a mem,
      because lra will not substitute such equiv memory in order to
      prevent access beyond allocated memory for paradoxical memory subreg.  */
   FOR_EACH_BB_FN (bb, cfun)
@@ -4776,7 +4776,7 @@ interesting_dest_for_shprep_1 (rtx set, basic_block call_dom)
   return dest;
 }
 
-/* If insn is interesting for parameter range-splitting shring-wrapping
+/* If insn is interesting for parameter range-splitting shrink-wrapping
    preparation, i.e. it is a single set from a hard register to a pseudo, which
    is live at CALL_DOM (if non-NULL, otherwise this check is omitted), or a
    parallel statement with only one such statement, return the destination.
diff --git a/gcc/ira.h b/gcc/ira.h
index a3bcbdc..a6c067d 100644
--- a/gcc/ira.h
+++ b/gcc/ira.h
@@ -64,7 +64,7 @@ struct target_ira
      class.  */
   enum reg_class x_ira_pressure_class_translate[N_REG_CLASSES];
 
-  /* Bigest pressure register class containing stack registers.
+  /* Biggest pressure register class containing stack registers.
      NO_REGS if there are no stack registers.  */
   enum reg_class x_ira_stack_reg_pressure_class;
 
-- 
1.9.3


Index Nav: [Date Index] [Subject Index] [Author Index] [Thread Index]
Message Nav: [Date Prev] [Date Next] [Thread Prev] [Thread Next]