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Re: [AArch64/GCC][18/N] Optimize epilogue when there is no frame pointer


sorry, attach patch.

ok for install?

thanks.

gcc/
   * config/aarch64/aarch64.c (aarch64_popwb_single_reg): New function.
   (aarch64_expand_epilogue): Optimize epilogue when !frame_pointer_needed.

gcc/testsuite/
   * gcc.target/aarch64/test_frame_1.c: Match optimized instruction sequences.
   * gcc.target/aarch64/test_frame_2.c: Likewise.
   * gcc.target/aarch64/test_frame_4.c: Likewise.
   * gcc.target/aarch64/test_frame_6.c: Likewise.
   * gcc.target/aarch64/test_frame_7.c: Likewise.
   * gcc.target/aarch64/test_frame_8.c: Likewise.
   * gcc.target/aarch64/test_frame_10.c: Likewise.


On 24/07/14 13:46, Jiong Wang wrote:
Like [17/N], we do same optimization on epilogue for !frame_pointer_needed.
this is the last of this aarch64 stack patch set.

    Improved testcases:
gcc.target/aarch64/test_frame_1.c
      gcc.target/aarch64/test_frame_2.c
      gcc.target/aarch64/test_frame_4.c
      gcc.target/aarch64/test_frame_6.c
      gcc.target/aarch64/test_frame_7.c
      gcc.target/aarch64/test_frame_8.c
      gcc.target/aarch64/test_frame_10.c


ok for install?

thanks.

gcc/
    * config/aarch64/aarch64.c (aarch64_popwb_single_reg): New function.
    (aarch64_expand_epilogue): Optimize epilogue when !frame_pointer_needed.

gcc/testsuite/
    * gcc.target/aarch64/test_frame_1.c: Match optimized instruction sequences.
    * gcc.target/aarch64/test_frame_2.c: Likewise.
    * gcc.target/aarch64/test_frame_4.c: Likewise.
    * gcc.target/aarch64/test_frame_6.c: Likewise.
    * gcc.target/aarch64/test_frame_7.c: Likewise.
    * gcc.target/aarch64/test_frame_8.c: Likewise.
    * gcc.target/aarch64/test_frame_10.c: Likewise.





From d1dc1b7e1c25b37aecf28967b4368422a9378d56 Mon Sep 17 00:00:00 2001
From: Jiong Wang <jiong.wang@arm.com>
Date: Tue, 17 Jun 2014 22:27:13 +0100
Subject: [PATCH 18/19] [AArch64/GCC][19/20] Optimize epilogue when there is
 no frame pointer

Like previous patch, we do same optimization on epilogue for
!frame_pointer_needed.

  Improved testcases:

  gcc.target/aarch64/test_frame_1.c
  gcc.target/aarch64/test_frame_2.c
  gcc.target/aarch64/test_frame_4.c
  gcc.target/aarch64/test_frame_6.c
  gcc.target/aarch64/test_frame_7.c
  gcc.target/aarch64/test_frame_8.c
  gcc.target/aarch64/test_frame_10.c

2014-06-16  Jiong Wang <jiong.wang@arm.com>
	    Marcus Shawcroft  <marcus.shawcroft@arm.com>

gcc/
  * config/aarch64/aarch64.c (aarch64_popwb_single_reg): New function.
  (aarch64_expand_epilogue): Optimize epilogue when !frame_pointer_needed.

gcc/testsuite/
  * gcc.target/aarch64/test_frame_1.c: Match optimized instruction sequences.
  * gcc.target/aarch64/test_frame_2.c: Likewise.
  * gcc.target/aarch64/test_frame_4.c: Likewise.
  * gcc.target/aarch64/test_frame_6.c: Likewise.
  * gcc.target/aarch64/test_frame_7.c: Likewise.
  * gcc.target/aarch64/test_frame_8.c: Likewise.
  * gcc.target/aarch64/test_frame_10.c: Likewise.
---
 gcc/config/aarch64/aarch64.c                     |   55 ++++++++++++++++++----
 gcc/testsuite/gcc.target/aarch64/test_frame_1.c  |    2 +
 gcc/testsuite/gcc.target/aarch64/test_frame_10.c |    2 +
 gcc/testsuite/gcc.target/aarch64/test_frame_2.c  |    2 +
 gcc/testsuite/gcc.target/aarch64/test_frame_4.c  |    2 +
 gcc/testsuite/gcc.target/aarch64/test_frame_6.c  |    2 +
 gcc/testsuite/gcc.target/aarch64/test_frame_7.c  |    2 +
 gcc/testsuite/gcc.target/aarch64/test_frame_8.c  |    2 +
 8 files changed, 59 insertions(+), 10 deletions(-)

diff --git a/gcc/config/aarch64/aarch64.c b/gcc/config/aarch64/aarch64.c
index 365fdd4..b884685 100644
--- a/gcc/config/aarch64/aarch64.c
+++ b/gcc/config/aarch64/aarch64.c
@@ -1943,6 +1943,23 @@ aarch64_pushwb_single_reg (enum machine_mode mode, unsigned regno,
   RTX_FRAME_RELATED_P (insn) = 1;
 }
 
+static void
+aarch64_popwb_single_reg (enum machine_mode mode, unsigned regno,
+			  HOST_WIDE_INT adjustment)
+{
+  rtx base_rtx = stack_pointer_rtx;
+  rtx insn, reg, mem;
+
+  reg = gen_rtx_REG (mode, regno);
+  mem = gen_rtx_POST_MODIFY (Pmode, base_rtx,
+			     plus_constant (Pmode, base_rtx, adjustment));
+  mem = gen_rtx_MEM (mode, mem);
+
+  insn = emit_move_insn (reg, mem);
+  add_reg_note (insn, REG_CFA_RESTORE, reg);
+  RTX_FRAME_RELATED_P (insn) = 1;
+}
+
 static rtx
 aarch64_gen_storewb_pair (enum machine_mode mode, rtx base, rtx reg, rtx reg2,
 			  HOST_WIDE_INT adjustment)
@@ -2381,7 +2398,6 @@ aarch64_expand_epilogue (bool for_sibcall)
   HOST_WIDE_INT fp_offset;
   rtx insn;
   rtx cfa_reg;
-  bool skip_wb = false;
 
   aarch64_layout_frame ();
 
@@ -2429,22 +2445,41 @@ aarch64_expand_epilogue (bool for_sibcall)
       cfa_reg = stack_pointer_rtx;
     }
 
-  aarch64_restore_callee_saves (DFmode, frame_pointer_needed ? 0 : fp_offset,
-				V0_REGNUM, V31_REGNUM, skip_wb);
-
   if (offset > 0)
     {
+      unsigned reg1 = cfun->machine->frame.wb_candidate1;
+      unsigned reg2 = cfun->machine->frame.wb_candidate2;
+      bool skip_wb = true;
+
       if (frame_pointer_needed)
+	fp_offset = 0;
+      else if (fp_offset
+	       || reg1 == FIRST_PSEUDO_REGISTER
+	       || (reg2 == FIRST_PSEUDO_REGISTER
+		   && offset >= 256))
+	skip_wb = false;
+
+      aarch64_restore_callee_saves (DImode, fp_offset, R0_REGNUM, R30_REGNUM,
+				    skip_wb);
+      aarch64_restore_callee_saves (DFmode, fp_offset, V0_REGNUM, V31_REGNUM,
+				    skip_wb);
+
+      if (skip_wb)
 	{
-	  aarch64_restore_callee_saves (DImode, 0, R0_REGNUM, R28_REGNUM,
-					skip_wb);
-	  aarch64_popwb_pair_reg (DImode, R29_REGNUM, R30_REGNUM, offset,
-				  cfa_reg);
+	  enum machine_mode mode1 = (reg1 <= R30_REGNUM) ? DImode : DFmode;
+
+	  if (reg2 == FIRST_PSEUDO_REGISTER)
+	    aarch64_popwb_single_reg (mode1, reg1, offset);
+	  else
+	    {
+	      if (reg1 != HARD_FRAME_POINTER_REGNUM)
+		cfa_reg = NULL;
+
+	      aarch64_popwb_pair_reg (mode1, reg1, reg2, offset, cfa_reg);
+	    }
 	}
       else
 	{
-	  aarch64_restore_callee_saves (DImode, fp_offset, R0_REGNUM,
-					R30_REGNUM, skip_wb);
 	  insn = emit_insn (gen_add2_insn (stack_pointer_rtx,
 					   GEN_INT (offset)));
 	  RTX_FRAME_RELATED_P (insn) = 1;
diff --git a/gcc/testsuite/gcc.target/aarch64/test_frame_1.c b/gcc/testsuite/gcc.target/aarch64/test_frame_1.c
index e9d04aa..5b3c0ab 100644
--- a/gcc/testsuite/gcc.target/aarch64/test_frame_1.c
+++ b/gcc/testsuite/gcc.target/aarch64/test_frame_1.c
@@ -14,4 +14,6 @@ t_frame_pattern (test1, 200, )
 t_frame_run (test1)
 
 /* { dg-final { scan-assembler-times "str\tx30, \\\[sp, -\[0-9\]+\\\]!" 2 } } */
+/* { dg-final { scan-assembler-times "ldr\tx30, \\\[sp\\\], \[0-9\]+" 3 } } */
+
 /* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/aarch64/test_frame_10.c b/gcc/testsuite/gcc.target/aarch64/test_frame_10.c
index b646a71..525b49e 100644
--- a/gcc/testsuite/gcc.target/aarch64/test_frame_10.c
+++ b/gcc/testsuite/gcc.target/aarch64/test_frame_10.c
@@ -16,4 +16,6 @@ t_frame_pattern_outgoing (test10, 480, "x19", 24, a[8], a[9], a[10])
 t_frame_run (test10)
 
 /* { dg-final { scan-assembler-times "stp\tx19, x30, \\\[sp, -\[0-9\]+\\\]!" 1 } } */
+/* { dg-final { scan-assembler-times "ldp\tx19, x30, \\\[sp\\\], \[0-9\]+" 1 } } */
+
 /* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/aarch64/test_frame_2.c b/gcc/testsuite/gcc.target/aarch64/test_frame_2.c
index b972664..6ec4088 100644
--- a/gcc/testsuite/gcc.target/aarch64/test_frame_2.c
+++ b/gcc/testsuite/gcc.target/aarch64/test_frame_2.c
@@ -15,4 +15,6 @@ t_frame_run (test2)
 
 
 /* { dg-final { scan-assembler-times "stp\tx19, x30, \\\[sp, -\[0-9\]+\\\]!" 1 } } */
+/* { dg-final { scan-assembler-times "ldp\tx19, x30, \\\[sp\\\], \[0-9\]+" 2 } } */
+
 /* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/aarch64/test_frame_4.c b/gcc/testsuite/gcc.target/aarch64/test_frame_4.c
index 5a9a919..ebfb290 100644
--- a/gcc/testsuite/gcc.target/aarch64/test_frame_4.c
+++ b/gcc/testsuite/gcc.target/aarch64/test_frame_4.c
@@ -14,4 +14,6 @@ t_frame_pattern (test4, 400, "x19")
 t_frame_run (test4)
 
 /* { dg-final { scan-assembler-times "stp\tx19, x30, \\\[sp, -\[0-9\]+\\\]!" 1 } } */
+/* { dg-final { scan-assembler-times "ldp\tx19, x30, \\\[sp\\\], \[0-9\]+" 2 } } */
+
 /* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/aarch64/test_frame_6.c b/gcc/testsuite/gcc.target/aarch64/test_frame_6.c
index 6056f57..b5ea7ee 100644
--- a/gcc/testsuite/gcc.target/aarch64/test_frame_6.c
+++ b/gcc/testsuite/gcc.target/aarch64/test_frame_6.c
@@ -15,4 +15,6 @@ t_frame_pattern (test6, 700, )
 t_frame_run (test6)
 
 /* { dg-final { scan-assembler-times "str\tx30, \\\[sp, -\[0-9\]+\\\]!" 2 } } */
+/* { dg-final { scan-assembler-times "ldr\tx30, \\\[sp\\\], \[0-9\]+" 3 } } */
+
 /* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/aarch64/test_frame_7.c b/gcc/testsuite/gcc.target/aarch64/test_frame_7.c
index 991860c..daa1f42 100644
--- a/gcc/testsuite/gcc.target/aarch64/test_frame_7.c
+++ b/gcc/testsuite/gcc.target/aarch64/test_frame_7.c
@@ -15,4 +15,6 @@ t_frame_pattern (test7, 700, "x19")
 t_frame_run (test7)
 
 /* { dg-final { scan-assembler-times "stp\tx19, x30, \\\[sp, -\[0-9\]+\\\]!" 1 } } */
+/* { dg-final { scan-assembler-times "ldp\tx19, x30, \\\[sp\\\], \[0-9\]+" 2 } } */
+
 /* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/aarch64/test_frame_8.c b/gcc/testsuite/gcc.target/aarch64/test_frame_8.c
index 4a4d93b..4ce630c 100644
--- a/gcc/testsuite/gcc.target/aarch64/test_frame_8.c
+++ b/gcc/testsuite/gcc.target/aarch64/test_frame_8.c
@@ -13,4 +13,6 @@ t_frame_pattern_outgoing (test8, 700, , 8, a[8])
 t_frame_run (test8)
 
 /* { dg-final { scan-assembler-times "str\tx30, \\\[sp, -\[0-9\]+\\\]!" 3 } } */
+/* { dg-final { scan-assembler-times "ldr\tx30, \\\[sp\\\], \[0-9\]+" 3 } } */
+
 /* { dg-final { cleanup-saved-temps } } */
-- 
1.7.9.5

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