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[msp430] fix addneghi and add split


Minor bugfixes.  Committed to head and 4.9 branch.

	* config/msp430/msp430.md (split): Don't allow subregs when
	splitting SImode adds.
	(andneghi): Fix subtraction logic.
	* config/msp430/predicates.md (msp430_nonsubreg_or_imm_operand): New.

Index: config/msp430/predicates.md
===================================================================
--- config/msp430/predicates.md	(revision 210652)
+++ config/msp430/predicates.md	(working copy)
@@ -70,11 +70,15 @@
 		     || INTVAL (op) == ~8
 		     || INTVAL (op) == ~(-1) "))))
 
 (define_predicate "msp430_nonsubreg_operand"
   (match_code "reg,mem"))
 
+(define_predicate "msp430_nonsubreg_or_imm_operand"
+  (ior (match_operand 0 "msp430_nonsubreg_operand")
+       (match_operand 0 "immediate_operand")))
+
 ; TRUE for constants which are bit positions for zero_extract
 (define_predicate "msp430_bitpos"
   (and (match_code "const_int")
        (match_test ("   INTVAL (op) >= 0
 		     && INTVAL (op) <= 15 "))))
Index: config/msp430/msp430.md
===================================================================
--- config/msp430/msp430.md	(revision 210652)
+++ config/msp430/msp430.md	(working copy)
@@ -359,14 +359,14 @@
 
 ; Split an SImode add into two HImode adds, keeping track of the carry
 ; so that gcc knows when it can and can't optimize away the two
 ; halves.
 (define_split
   [(set (match_operand:SI          0 "msp430_nonsubreg_operand")
-	(plus:SI (match_operand:SI 1 "nonimmediate_operand")
-		 (match_operand:SI 2 "general_operand")))
+	(plus:SI (match_operand:SI 1 "msp430_nonsubreg_operand")
+		 (match_operand:SI 2 "msp430_nonsubreg_or_imm_operand")))
    ]
   ""
   [(parallel [(set (match_operand:HI 3 "nonimmediate_operand" "=&rm")
 		   (plus:HI (match_dup 4)
 			    (match_dup 5)))
 	      (set (reg:BI CARRY)
@@ -1314,15 +1314,15 @@
   [(set (match_operand:HI                 0 "register_operand" "=r")
 	(and:HI (neg:HI (match_operand:HI 1 "register_operand"  "r"))
 		(match_operand            2 "immediate_operand" "n")))]
   ""
   "*
     if (REGNO (operands[0]) != REGNO (operands[1]))
-      return \"MOV.W\t%1, %0 { SUB.W\t#0, %0 { AND.W\t%2, %0\";
+      return \"MOV.W\t%1, %0 { INV.W\t%0 { INC.W\t%0 { AND.W\t%2, %0\";
     else
-      return \"SUB.W\t#0, %0 { AND.W\t%2, %0\";
+      return \"INV.W\t%0 { INC.W\t%0 { AND.W\t%2, %0\";
   "
   )
 
 (define_insn "mulhisi3"
   [(set (match_operand:SI                          0 "register_operand" "=r")
 	(mult:SI (sign_extend:SI (match_operand:HI 1 "register_operand" "%0"))


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