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[PATCH 1/3, x86] X86 Silvermont vector cost model tune
- From: Evgeny Stupachenko <evstupac at gmail dot com>
- To: Uros Bizjak <ubizjak at gmail dot com>
- Cc: "H.J. Lu" <hjl dot tools at gmail dot com>, GCC Patches <gcc-patches at gcc dot gnu dot org>, uros at gcc dot gnu dot org
- Date: Tue, 15 Apr 2014 20:06:04 +0400
- Subject: [PATCH 1/3, x86] X86 Silvermont vector cost model tune
- Authentication-results: sourceware.org; auth=none
Hi,
I've separated the patch into 3.
The patch passes x86 bootstrap.
1st part:
2014-04-15 Evgeny Stupachenko <evstupac@gmail.com>
* config/i386/i386.c (slm_cost): Fixing vec_to_scalar_cost for
Silvermont according latency table.
(intel_cost): Ditto.
diff --git a/gcc/config/i386/i386.c b/gcc/config/i386/i386.c
index f2e6957..bf4d576 100644
--- a/gcc/config/i386/i386.c
+++ b/gcc/config/i386/i386.c
@@ -1738,7 +1738,7 @@ struct processor_costs slm_cost = {
1, /* scalar load_cost. */
1, /* scalar_store_cost. */
1, /* vec_stmt_cost. */
- 1, /* vec_to_scalar_cost. */
+ 4, /* vec_to_scalar_cost. */
1, /* scalar_to_vec_cost. */
1, /* vec_align_load_cost. */
2, /* vec_unalign_load_cost. */
@@ -1815,7 +1815,7 @@ struct processor_costs intel_cost = {
1, /* scalar load_cost. */
1, /* scalar_store_cost. */
1, /* vec_stmt_cost. */
- 1, /* vec_to_scalar_cost. */
+ 4, /* vec_to_scalar_cost. */
1, /* scalar_to_vec_cost. */
1, /* vec_align_load_cost. */
2, /* vec_unalign_load_cost. */
Evgeny
On Thu, Mar 6, 2014 at 12:58 AM, Evgeny Stupachenko <evstupac@gmail.com> wrote:
> slm_cost/intel_cost and TARGET_SLOW_PSHUFB are just preparation to a
> next vectorization patch.
> Changes in ix86_add_stmt_cost gives real performance to Silvermont.
> Let's move all to stage1.
>
> On Wed, Mar 5, 2014 at 9:29 PM, Uros Bizjak <ubizjak@gmail.com> wrote:
>> On Wed, Mar 5, 2014 at 5:46 PM, H.J. Lu <hjl.tools@gmail.com> wrote:
>>> On Wed, Mar 5, 2014 at 7:58 AM, Evgeny Stupachenko <evstupac@gmail.com> wrote:
>>>> Hi,
>>>>
>>>> The patch is for x86 Silvermont.
>>>> It improves x86 Silvermont vector cost model.
>>>> It gives +20% on facerec spec on Silvermont.
>>>> It passes make check and bootstrap on x86.
>>>>
>>>> Is this patch ok for stage1?
>>>>
>>>> ChangeLog:
>>>>
>>>> 2014-03-05 Evgeny Stupachenko <evstupac@gmail.com>
>>>>
>>>> * config/i386/x86-tune.def (TARGET_SLOW_PSHUFB): Target for slow byte
>>>> shuffle on some x86 architectures.
>>>> * config/i386/i386.h (TARGET_SLOW_PSHUFB): Ditto.
>>>> * config/i386/i386.c (processor_costs): Fixing vec_to_scalar_cost for
>>>> Silvermont according latency table.
>>>> (expand_vec_perm_even_odd_1): Avoid byte shuffles in architectures
>>>> where they are slow (TARGET_SLOW_PSHUFB).
>>>> (x86_add_stmt_cost): Fixing vector cost model for Silvermont.
>>>>
>>>> Thanks,
>>>> Evgeny
>>>
>>> There are 3 separate changes in this patch:
>>>
>>> 1. Update slm_cost, which doesn't have a ChangeLog entry.
>>> 2. Add TARGET_SLOW_PSHUFB.
>>> 3. Update ix86_add_stmt_cost.
>>>
>>> I suggest you break it into 3 independent patches.
>>
>> I think that slm_cost/intel_cost and TARGET_SLOW_PSHUFB changes can
>> still go into mainline at this stage since they are trivial tuning
>> changes that should not destabilize the compiler.
>>
>> The ix86_add_stmt_cost should wait for stage 1.
>>
>> Uros.