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Re: [AArch64] Logical vector shift right conformance
- From: Marcus Shawcroft <marcus dot shawcroft at gmail dot com>
- To: Alex Velenko <Alex dot Velenko at arm dot com>
- Cc: "gcc-patches at gcc dot gnu dot org" <gcc-patches at gcc dot gnu dot org>, Marcus Shawcroft <Marcus dot Shawcroft at arm dot com>, jakub at redhat dot com
- Date: Thu, 20 Mar 2014 12:59:27 +0000
- Subject: Re: [AArch64] Logical vector shift right conformance
- Authentication-results: sourceware.org; auth=none
- References: <530C8580 dot 9020400 at arm dot com>
On 25 February 2014 11:58, Alex Velenko <Alex.Velenko@arm.com> wrote:
> Hi,
>
> This patch fixes a bug in vshr_n_u64 and vshrd_n_u64 intrinsic
> behavior in case of shift by 64. Shift by 64 is strictly defined in ACLE to
> use ushr instruction intended by those intrinsics.
>
> The testcase provided also tests the behavior for intrinsics mentioned
> above with values other then 64. Besides, the test checks that an illeagal
> ushr shift by 0 is not generated, expecting the test to compile and run
> correctly generating instructions other than ushr.
>
> The patch was tested for LE and BE with no regressions.
>
> Is given patch ok for stage-4?
I think this is OK for stage-4, but leave 24h before committing to
allow the RM's opportunity to object / comment.
Cheers
/Marcus