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Re: [Patch] Try to peephole2 QI *4 into SI on i386
- From: lin zuojian <manjian2006 at gmail dot com>
- To: Andrew Pinski <pinskia at gmail dot com>
- Cc: GCC Patches <gcc-patches at gcc dot gnu dot org>
- Date: Tue, 4 Mar 2014 11:44:06 +0800
- Subject: Re: [Patch] Try to peephole2 QI *4 into SI on i386
- Authentication-results: sourceware.org; auth=none
- References: <20140303130203 dot GF10357 at ubuntu> <CA+=Sn1=OAdNSaWi78OJZfk+5PdLmMXYjeVCEsWORe_Jq71gOsQ at mail dot gmail dot com>
On Mon, Mar 03, 2014 at 07:19:51PM -0800, Andrew Pinski wrote:
> On Mon, Mar 3, 2014 at 5:02 AM, lin zuojian <manjian2006@gmail.com> wrote:
>
> Testcase?
The test case is the same with
http://gcc.gnu.org/bugzilla/show_bug.cgi?id=23684.
> How about making a generic pass which does this?
Maybe GIMPLE should add a pass about it.Now slp pass has hadled it,but
only available in O3.
>
> See http://gcc.gnu.org/bugzilla/show_bug.cgi?id=23684 also. At the
> same time this can be used to do the store pair optimization for
> ARM/AARCH64 too.
>
> Thanks,
> Andrew
>
>
> >
> > ---
> > gcc/config/i386/i386.md | 49 +++++++++++++++++++++++++++++++++++++++++++++++++
> > 1 file changed, 49 insertions(+)
> >
> > diff --git a/gcc/config/i386/i386.md b/gcc/config/i386/i386.md
> > index b9f1320..86ab025 100644
> > --- a/gcc/config/i386/i386.md
> > +++ b/gcc/config/i386/i386.md
> > @@ -18535,6 +18535,55 @@
> > [(set_attr "type" "other")
> > (set_attr "length" "3")])
> >
> > +(define_peephole2
> > + [(set (mem:QI (match_operand 0 "register_operand"))
> > + (match_operand 1 "const_int_operand"))
> > + (set (mem:QI (plus (match_dup 0)
> > + (const_int 1)))
> > + (match_operand 2 "const_int_operand"))
> > + (set (mem:QI (plus (match_dup 0)
> > + (const_int 2)))
> > + (match_operand 3 "const_int_operand"))
> > + (set (mem:QI (plus (match_dup 0)
> > + (const_int 3)))
> > + (match_operand 4 "const_int_operand"))]
> > + ""
> > + [(set (mem:SI (match_dup 0))
> > + (match_operand 5 "const_int_operand"))]
> > +{
> > + int32_t _const = (INTVAL(operands[1]) & 0xff) | (((INTVAL(operands[2])) & 0xff) << 8)
> > + | (((INTVAL(operands[3])) & 0xff) << 16) | (((INTVAL(operands[4])) & 0xff) << 24);
> > + operands[5] = gen_rtx_CONST_INT (SImode, _const);
> > +}
> > +)
> > +
> > +(define_peephole2
> > + [(set (mem:QI (plus (match_operand 0 "register_operand")
> > + (match_operand 6 "const_int_operand")))
> > + (match_operand 1 "const_int_operand"))
> > + (set (mem:QI (plus (match_dup 0)
> > + (match_operand 7 "const_int_operand")))
> > + (match_operand 2 "const_int_operand"))
> > + (set (mem:QI (plus (match_dup 0)
> > + (match_operand 8 "const_int_operand")))
> > + (match_operand 3 "const_int_operand"))
> > + (set (mem:QI (plus (match_dup 0)
> > + (match_operand 9 "const_int_operand")))
> > + (match_operand 4 "const_int_operand"))]
> > + ""
> > + [(set (mem:SI (match_dup 0))
> > + (match_operand 5 "const_int_operand"))]
> > +{
> > + if ((INTVAL(operands[7]) - INTVAL(operands[6]) != 1)
> > + && (INTVAL(operands[8]) - INTVAL(operands[7]) != 1)
> > + && (INTVAL(operands[9]) - INTVAL(operands[8]) != 1))
> > + FAIL;
> > + int32_t _const = (INTVAL(operands[1]) & 0xff) | (((INTVAL(operands[2])) & 0xff) << 8)
> > + | (((INTVAL(operands[3])) & 0xff) << 16) | (((INTVAL(operands[4])) & 0xff) << 24);
> > + operands[5] = gen_rtx_CONST_INT (SImode, _const);
> > +}
> > +)
> > +
> > (include "mmx.md")
> > (include "sse.md")
> > (include "sync.md")
> > --
> > 1.8.3.2
> >
> >
> > ----- End forwarded message -----