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Re: [PATCH,rs6000] Add -maltivec={le,be} options
- From: Bill Schmidt <wschmidt at linux dot vnet dot ibm dot com>
- To: "Joseph S. Myers" <joseph at codesourcery dot com>
- Cc: gcc-patches at gcc dot gnu dot org, dje dot gcc at gmail dot com
- Date: Tue, 07 Jan 2014 16:06:15 -0600
- Subject: Re: [PATCH,rs6000] Add -maltivec={le,be} options
- Authentication-results: sourceware.org; auth=none
- References: <1389128467 dot 18332 dot 10 dot camel at gnopaine> <Pine dot LNX dot 4 dot 64 dot 1401072147520 dot 27342 at digraph dot polyomino dot org dot uk>
On Tue, 2014-01-07 at 21:51 +0000, Joseph S. Myers wrote:
> On Tue, 7 Jan 2014, Bill Schmidt wrote:
>
> > +@item -maltivec=be
> > +@opindex maltivec=be
> > +Generate Altivec instructions using big-endian element order,
> > +regardless of whether the target is big- or little-endian.
> > +
> > +@item -maltivec=le
> > +@opindex maltivec=le
> > +Generate Altivec instructions using little-endian element order,
> > +regardless of whether the target is big- or little-endian. This
> > +option is currently ignored for big-endian targets, but may be enabled
> > +in the future.
>
> I don't understand what "using big-endian element order" or "using
> little-endian element order" means. Is this about the interpretation of
> element numbers in AltiVec intrinsics? (In GNU C vector indexing with
> array notation, GENERIC, GIMPLE and RTL, vector element numbers are always
> in memory order like in arrays, so a command-line option like this
> *shouldn't* affect anything other than intrinsics. Cf. the ARM NEON code
> that deals with flipping element order conventions for big endian so that
> intrinsics can follow the ARM convention while GNU C, GENERIC, GIMPLE and
> RTL follow the convention that the architecture-independent compiler
> expects.)
>
Yes, sorry for not being more clear. This is indeed for interpretation
of element numbers in Altivec intrinsics such as vec_splat, vec_extract,
vec_insert, and so forth. By default these will match array element
order for the target endianness. But with -maltivec=be for a little
endian target, we will force use of big-endian element order (matching
the behavior of the underlying hardware instructions).
There are certain VSX load and store instructions that assume big-endian
ordering of vector elements in a register regardless of target
endianness. Applications developed for Power BE that use these
instructions via intrinsics will be easier to port to Power LE with
-maltivec=be.