Re: [PATCH 2/6] Andes nds32: machine description of nds32 porting (1).

[Richard Sandiford <rdsandiford at googlemail dot com>]

Chung-Ju Wu <jasonwucj@gmail.com> writes:
> On 10/6/13 5:36 PM, Richard Sandiford wrote:
>> Thanks for the updates.
>> 
>> Chung-Ju Wu <jasonwucj@gmail.com> writes:
>>>
>>> Now we remove all "use"s and "clobber"s from parallel rtx and
>>> use predicate function to check stack push/pop operation.
>>> Furthermore, once I remove unspec rtx as you suggested,
>>> I notice gcc is aware of the def-use dependency and it wouldn't
>>> perform unexpected register renaming.  So I think it was my
>>> faulty design of placing unspec/use/clobber within parallel rtx.
>> 
>> FWIW, it'd probably be better for nds32_valid_stack_push_pop to check
>> all the SETs in the PARALLEL, like nds32_valid_multiple_load_store does.
>> They could share a subroutine that checks for conesecutive loads and stores.
>> I.e. something like:
>> 
>> static bool
>> nds32_valid_multiple_load_store_1 (rtx op, bool load_p, int start, int end)
>> {
>>   ...
>> }
>> 
>> bool
>> nds32_valid_multiple_load_store (rtx op, bool load_p)
>> {
>>   return nds32_valid_multiple_load_store_1 (op, load_p, 0, XVECLEN (op, 0));
>> }
>> 
>> bool
>> nds32_valid_multiple_push_pop (rtx op, bool load_p)
>> {
>>   ...handle $lp, $gp and $fp cases, based on cframe->...
>>   if (!nds32_valid_multiple_load_store_1 (op, load_p, i, count - 1))
>>     return false;
>>   ...check last element...
>> }
>> 
>
> Now I follow your suggestion to implement a subroutine
> nds32_consecutive_registers_load_store_p().
> Both nds32_valid_multiple_load_store() and nds32_valid_stack_push_pop()
> can share this subroutine to check consecutive load/store behavior.
>
> A revised-3 patch for nds32.c is attached.

Looks good to me, thanks.  FWIW, I was wondering if we could simplify things
by making the order of the SETs in the PARALLEL the same for push and pop,
but it's probably not much of a win.

Thanks,
Richard