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[AArch64] Use "multiple" for type, where more than one instruction is used for a move
- From: James Greenhalgh <james dot greenhalgh at arm dot com>
- To: gcc-patches at gcc dot gnu dot org
- Cc: marcus dot shawcroft at arm dot com, richard dot earnshaw at arm dot com, ramana dot radhakrishnan at arm dot com
- Date: Fri, 6 Sep 2013 14:46:10 +0100
- Subject: [AArch64] Use "multiple" for type, where more than one instruction is used for a move
- Authentication-results: sourceware.org; auth=none
Hi,
We could introduce a whole new type for insns which generate two moves,
but we have already introduced a "multiple" classification for
types in the ARM backend, so use that in place of "mov_reg" where
appropriate.
Regression tested on aarch64-none-elf and arm-none-eabi with no
regressions.
OK?
Thanks,
James
---
gcc/
2013-09-06 James Greenhalgh <james.greenhalgh@arm.com>
* config/aarch64/aarch64.md
(*movti_aarch64): Use "multiple" for type where v8type is "move2".
(*movtf_aarch64): Likewise.
* config/arm/arm.md
(thumb1_movdi_insn): Use "multiple" for type where more than one
instruction is used for a move.
(*arm32_movhf): Likewise.
(*thumb_movdf_insn): Likewise.
diff --git a/gcc/config/aarch64/aarch64.md b/gcc/config/aarch64/aarch64.md
index db6aa1d3fa15e17095ba26a64e020d098e9fa6c0..96705862de6b53322828fd60df15207af4b2ed61 100644
--- a/gcc/config/aarch64/aarch64.md
+++ b/gcc/config/aarch64/aarch64.md
@@ -906,7 +906,7 @@ (define_insn "*movti_aarch64"
str\\t%q1, %0"
[(set_attr "v8type" "move2,fmovi2f,fmovf2i,*, \
load2,store2,store2,fpsimd_load,fpsimd_store")
- (set_attr "type" "mov_reg,f_mcr,f_mrc,*, \
+ (set_attr "type" "multiple,f_mcr,f_mrc,*, \
load2,store2,store2,f_loadd,f_stored")
(set_attr "simd_type" "*,*,*,simd_move,*,*,*,*,*")
(set_attr "mode" "DI,DI,DI,TI,DI,DI,DI,TI,TI")
@@ -1024,7 +1024,7 @@ (define_insn "*movtf_aarch64"
ldp\\t%0, %H0, %1
stp\\t%1, %H1, %0"
[(set_attr "v8type" "logic,move2,fmovi2f,fmovf2i,fconst,fconst,fpsimd_load,fpsimd_store,fpsimd_load2,fpsimd_store2")
- (set_attr "type" "logic_reg,mov_reg,f_mcr,f_mrc,fconstd,fconstd,\
+ (set_attr "type" "logic_reg,multiple,f_mcr,f_mrc,fconstd,fconstd,\
f_loadd,f_stored,f_loadd,f_stored")
(set_attr "mode" "DF,DF,DF,DF,DF,DF,TF,TF,DF,DF")
(set_attr "length" "4,8,8,8,4,4,4,4,4,4")
diff --git a/gcc/config/arm/arm.md b/gcc/config/arm/arm.md
index 6c0fbf44288c9f6e077fe2d9836cd5c1e2042a0a..fd0b1cbdccd23ad4d18be50417c7532b29840b91 100644
--- a/gcc/config/arm/arm.md
+++ b/gcc/config/arm/arm.md
@@ -6141,7 +6141,7 @@ (define_insn "*thumb1_movdi_insn"
}
}"
[(set_attr "length" "4,4,6,2,2,6,4,4")
- (set_attr "type" "multiple,mov_reg,multiple,load2,store2,load2,store2,mov_reg")
+ (set_attr "type" "multiple,multiple,multiple,load2,store2,load2,store2,multiple")
(set_attr "pool_range" "*,*,*,*,*,1018,*,*")]
)
@@ -7221,7 +7221,7 @@ (define_insn "*arm32_movhf"
}
"
[(set_attr "conds" "unconditional")
- (set_attr "type" "load1,store1,mov_reg,mov_reg")
+ (set_attr "type" "load1,store1,mov_reg,multiple")
(set_attr "length" "4,4,4,8")
(set_attr "predicable" "yes")]
)
@@ -7466,7 +7466,7 @@ (define_insn "*thumb_movdf_insn"
}
"
[(set_attr "length" "4,2,2,6,4,4")
- (set_attr "type" "multiple,load2,store2,load2,store2,mov_reg")
+ (set_attr "type" "multiple,load2,store2,load2,store2,multiple")
(set_attr "pool_range" "*,*,*,1018,*,*")]
)