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[Patch,AArch64] Support SISD Shifts (SHL/USHR/SSHL/USHL/SSHR)
- From: Vidya Praveen <vidyapraveen at arm dot com>
- To: gcc-patches at gcc dot gnu dot org
- Cc: marcus dot shawcroft at arm dot com
- Date: Tue, 20 Aug 2013 16:01:59 +0100
- Subject: [Patch,AArch64] Support SISD Shifts (SHL/USHR/SSHL/USHL/SSHR)
Hello,
This patch supports SISD shift instructions SHL/USHR/SSHR/SSHL/USHL for
SImode and DImode. This patch also refactors the integer shifts pattern
"<optab><mode>3_insn". Pattern for rotate is moved out as ror<mode>3_insn.
Shift patterns (aarch64_{lshr|ashl|ashr}_sisd_or_int_{si|di}3) support
both SIMD registers and general purpose registers with the shift quantity
either as variable or literal. Since there are no SISD instructions for
right shifts, the instruction SSHL and USHL are used with shift operand
negated using NEG in order reverse the direction. This is done by
insisting on splitting (after reload) in to neg and UNSPEC_SISD_USHL or
UNSPEC_SISD_SSHL or UNSPEC_USHL_S2 or UNSPEC_SSHL_S2 pattern. Since there
are no SISD variants of shift instructions available for SImode, the SIMD
variants of corresponsing instructions are used with 2S size by taking
one lane alone in to cosideration and ignoring other.
This patch also introduces a predicate aarch64_simd_register to help in
splitting patterns. Tests for both newly introduced instructions as well
as for the integer instructions are included.
Tested and no new regressions.
OK for trunk?
Regards
VP
---
gcc/ChangeLog
2013-08-20 Vidya Praveen <vidyapraveen@arm.com>
* config/aarch64/aarch64.md (unspec): Add UNSPEC_SISD_SSHL,
UNSPEC_SISD_USHL, UNSPEC_USHL_2S, UNSPEC_SSHL_2S, UNSPEC_SISD_NEG.
(<optab><mode>3_insn): Remove.
(aarch64_ashl_sisd_or_int_<mode>3): New Pattern.
(aarch64_lshr_sisd_or_int_<mode>3): Likewise.
(aarch64_ashr_sisd_or_int_<mode>3): Likewise.
(define_split for aarch64_lshr_sisd_or_int_di3): Likewise.
(define_split for aarch64_lshr_sisd_or_int_si3): Likewise.
(define_split for aarch64_ashr_sisd_or_int_di3): Likewise.
(define_split for aarch64_ashr_sisd_or_int_si3): Likewise.
(aarch64_sisd_ushl, aarch64_sisd_sshl): Likewise.
(aarch64_ushl_2s, aarch64_sshl_2s, aarch64_sisd_neg_qi): Likewise.
(ror<mode>3_insn): Likewise.
* config/aarch64/predicates.md (aarch64_simd_register): New.
gcc/testsuite/ChangeLog
2013-08-20 Vidya Praveen <vidyapraveen@arm.com>
* gcc.target/aarch64/scalar_shift_1.c: New.