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Re: [PATCH i386 1/8] [AVX512] Adjust register classes.


On Wed, Jul 24, 2013 at 8:27 PM, Kirill Yukhin <kirill.yukhin@gmail.com> wrote:
> Hello,
> By this patch I am starting series of patches toward Intel (R) AVX-512 and SHA (see [1])
> extensions enabling in GCC.
> I've already submitted corresponding patches to BinUtils (see [2],[3]).
>
> This patch adds comand-line options for avx512* use and relevant cpuid bits
> detection. Vector registers are now 512-bit wide, so support for new modes
> (e.g. V16SF) is added. AVX512F introduce new 16 registers zmm16-zmm31. Some
> instructions are now have EVEX encoding and can now use those new registers while
> old instructions can't. We introduce new register class for them. We also add
> new constraint "v" which allows zmm0-zmm31. We can't extend "x" constraint
> because it's exposed in inline asm, and so may break some inline asm if we
> assign e. g. xmm21 to non-evex encodable instruction.  Idea is to replace all
> uses of "x" for evex-encodable instructions with "v". And allow only scalar and
> 512-bit modes for registers 16+ in ix86_hard_regno_mode_ok. We update move
> instructions to use evex-encodable versions of instructions for AVX512F to
> allow usage of new registers. Main problem is with vector mov<mode>_internal
> in sse.md. In AVX512F we have some instructions reading/writing e. g. ymm16+
> (for exmaple vinsert64x4/vextract64x4),but there in no ymm mov instruction
> with evex encoding, so we have to use insert/extract instead.
>
> Testing:
>  - Bootstrap passing.
>  - No regressions on existing tests
>  - Spec2006 built successfully with new flags
>  - Spec2006 is currently in run under simulator and I'll report if any issues arise

Did you test the patch in isolation, so it won't break bisecting?

> Is it ok to install to trunk?

Are you sure that the patch is self-sufficient? At least definition
for shuffletype mode attribute is missing. The changes for sseinsnmode
attribute are also missing.

Uros.


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