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Re: [PATCH, rs6000, libitm] Enable Hardware Transactional Memory (HTM) support on Power


On Mon, Jul 15, 2013 at 08:44:12PM +0200, Jakub Jelinek wrote:
> On Mon, Jul 15, 2013 at 12:25:58PM -0500, Peter Bergner wrote:
> > On Mon, 2013-07-15 at 11:55 -0400, David Edelsohn wrote:
> > > Thanks for the explanation.  Leave it in.
> > > 
> > > Jakub was asking about the status of the HTM patch and support, so
> > > please check it in.
> > 
> > Ok, committed to mainline (after another bootstrap) as revision 200960.
> > Thanks!
> 
> Looking at the patch, you've changed FIRST_PSEUDO_REGISTER (internal gcc
> thing, so fine), but that also changed DWARF_FRAME_REGISTER which was
> computed based on FIRST_PSEUDO_REGISTER.  Isn't that an ABI break in the
> unwinder (think about having parts of unwinder linked from different
> versions of libgcc)?
> Can't we just tweak DWARF_FRAME_REGISTER not to include those registers?

I'd say something like (but, untested and can't test it right now (and no
access to power8 anyway)):

2013-07-15  Jakub Jelinek  <jakub@redhat.com>

	* config/rs6000/rs6000.h (FIRST_PSEUDO_REGISTERS): Mention HTM
	registers in the comment.
	(DWARF_FRAME_REGISTERS): Subtract also the 3 HTM registers.

--- gcc/config/rs6000/rs6000.h.jj	2013-07-15 21:08:02.000000000 +0200
+++ gcc/config/rs6000/rs6000.h	2013-07-15 21:11:06.846718216 +0200
@@ -892,15 +892,17 @@ enum data_align { align_abi, align_opt,
    in inline functions.
 
    Another pseudo (not included in DWARF_FRAME_REGISTERS) is soft frame
-   pointer, which is eventually eliminated in favor of SP or FP.  */
+   pointer, which is eventually eliminated in favor of SP or FP.
 
+   The 3 HTM registers aren't also included in DWARF_FRAME_REGISTERS.  */
+   
 #define FIRST_PSEUDO_REGISTER 117
 
 /* This must be included for pre gcc 3.0 glibc compatibility.  */
 #define PRE_GCC3_DWARF_FRAME_REGISTERS 77
 
 /* Add 32 dwarf columns for synthetic SPE registers.  */
-#define DWARF_FRAME_REGISTERS ((FIRST_PSEUDO_REGISTER - 1) + 32)
+#define DWARF_FRAME_REGISTERS ((FIRST_PSEUDO_REGISTER - 4) + 32)
 
 /* The SPE has an additional 32 synthetic registers, with DWARF debug
    info numbering for these registers starting at 1200.  While eh_frame


	Jakub


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