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Re: RFA: patch to build GCC for arm with LRA
- From: Vladimir Makarov <vmakarov at redhat dot com>
- To: Yvan Roux <yvan dot roux at linaro dot org>
- Cc: Richard Earnshaw <rearnsha at arm dot com>, gcc-patches <gcc-patches at gcc dot gnu dot org>, "rdsandiford at googlemail dot com" <rdsandiford at googlemail dot com>
- Date: Fri, 05 Jul 2013 19:12:51 -0400
- Subject: Re: RFA: patch to build GCC for arm with LRA
- References: <51CC6077 dot 6050401 at redhat dot com> <8738s3cyx5 dot fsf at sandifor-thinkpad dot stglab dot manchester dot uk dot ibm dot com> <51CC6908 dot 1040005 at redhat dot com> <51CC6D6E dot 5020708 at arm dot com> <51CC6F56 dot 1060809 at redhat dot com> <51CC720B dot 5090501 at arm dot com> <51CC748A dot 40807 at redhat dot com> <CAD57uCfhvW8AQ3FdybaNFeMMXR1ikBz8fJWgqFNJ2dW14NVdXQ at mail dot gmail dot com>
On 13-07-05 8:43 AM, Yvan Roux wrote:
Hi,
for AArch64 it is also needed to take into account SIGN_EXTRACT in the
set_address_base and set_address_index routines, as we acan encounter
that kind of insn for instance :
(insn 29 27 5 7 (set (mem:SI (plus:DI (sign_extract:DI (mult:DI
(subreg:DI (reg/v:SI 76 [ elt ]) 0)
...
OK.
with the attached patch and the LRA enabled, compiler now bootstrap
but I've few regressions in the testsuite,
It seems ok to me but I am confused of the following change:
set_address_base (struct address_info *info, rtx *loc, rtx *inner)
{
- if (GET_CODE (*inner) == LO_SUM)
+ if (GET_CODE (*inner) == SIGN_EXTRACT)
+ inner = strip_address_mutations (&XEXP (*inner, 0));
+
+ if (GET_CODE (*inner) == LO_SUM || GET_CODE (*inner) == MULT)
inner = strip_address_mutations (&XEXP (*inner, 0));
gcc_checking_assert (REG_P (*inner)
|| MEM_P (*inner)
base address should not contain MULT (which you added). It is
controlled by the result of must_be_index_p. So set_address_base should
not have code for MULT and you need to change must_be_index_p in a way
that set_address_base is not called for MULT.
gcc.c/torture/execute/fp-cmp-4l.c for instance. I was looking at these
issues before submitting a complete AArch64 LRA enabling patch, but
as you are speaking about that...
Valdimir, for the ARM target I already had the ASHIFTRT and LSHIFTRT
addition on my side, but still had an ICE during bootstrap with LRA
when compiling fixed-bit.c (the Max number of generated reload insns
we talk about already) is it working for you ?
I did not check thumb I guess. If what you are asking about the problem
you sent me about 2 weeks ago, I guess one solution would be putting
if (lra_in_progress)
return NO_REGS;
at the beginning of arm/targhooks.c::default_secondary_reload. LRA is
smart enough to figure out what to do from constraints in most cases of
when reload needs secondary_reload. In arm case,
default_secondary_reload only confuses LRA.
I had no time to test this change, but it solves LRA cycling for the
test case you sent me.