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Re: [PATCH][ARM][11/n] Partial IT block deprecation in ARMv8 AArch32 - final arm.md changes


On 21/06/13 11:53, Kyrylo Tkachov wrote:
Hi all,

This is the final patch in the series. It adjusts patterns in arm.md that do
arithmetic operations and comparisons. We add alternatives for 16-bit
encodings to the patterns. Some alternatives and patterns are disabled for
arm_restrict_it or their cond_exec variants.

The "Pd" constraint is relaxed to match for any Thumb target, not just Thumb1,
because the 0<= i <=7 range comes in handy in the add and subtract patterns. A
new Pz constraint is created that is needed to define the (rsb rd, rn, #0)
variant of subtraction, the only variant of rsb that can be encoded in 16
bits.


Bootstrapped on a Cortex-A15, tested on model and qemu with ARMv7 and ARMv8
architecture levels.

Ok for trunk?

Thanks,
Kyrill


2013-06-21  Kyrylo Tkachov  <kyrylo.tkachov@arm.com>

	* config/arm/constraints.md (Pd): Allow TARGET_THUMB
	instead of TARGET_THUMB1.
	(Pz): New constraint.
	* config/arm/arm.md (arm_addsi3): Add alternatives for 16-bit
encodings.
	(compare_negsi_si): Likewise.
	(compare_addsi2_op0): Likewise.
	(compare_addsi2_op1): Likewise.
	(addsi3_carryin_<optab>): Likewise.
	(addsi3_carryin_alt2_<optab>): Likewise.
	(addsi3_carryin_shift_<optab>): Disable cond_exec variant
	for arm_restrict_it.
	(subsi3_carryin): Likewise.
	(arm_subsi3_insn): Add alternatives for 16-bit encoding.
	(minmax_arithsi): Disable for arm_restrict_it.
	(minmax_arithsi_non_canon): Adjust for arm_restrict_it.
	(satsi_<SAT:code>): Disable cond_exec variant for arm_restrict_it.
	(satsi_<SAT:code>_shift): Likewise.
	(arm_shiftsi3): Add alternative for 16-bit encoding.
	(arm32_movhf): Disable for arm_restrict_it.
	(arm_cmpdi_unsigned): Add alternatives for 16-bit encoding.
	(arm_movtas_ze): Disable cond_exec variant for arm_restrict_it.




  (define_insn_and_split "*arm_addsi3"
- [(set (match_operand:SI 0 "s_register_operand" "=rk, r,k, r,r, k, r, k,k,r, k, r") - (plus:SI (match_operand:SI 1 "s_register_operand" "%0, rk,k, r,rk,k, rk,k,r,rk,k, rk") - (match_operand:SI 2 "reg_or_int_operand" "rk, rI,rI,k,Pj,Pj,L, L,L,PJ,PJ,?n")))] + [(set (match_operand:SI 0 "s_register_operand" "=rk,l,l,l,r,k, r,r, k, r, k,k,r, k, r") + (plus:SI (match_operand:SI 1 "s_register_operand" "%0,l,0,l,rk,k, r,rk,k, rk,k,r,rk,k, rk") + (match_operand:SI 2 "reg_or_int_operand" "rk,l,Py,Pd,rI,rI,k,Pj,Pj,L, L,L,PJ,PJ,?n")))]

Please make sure you keep the alternatives correctly aligned. With this many alternatives matching up the constraints is becoming a nightmare if they aren't in columns

 (define_insn "*arm_shiftsi3"
-  [(set (match_operand:SI   0 "s_register_operand" "=r")
+  [(set (match_operand:SI   0 "s_register_operand" "=l,r")
 	(match_operator:SI  3 "shift_operator"
-	 [(match_operand:SI 1 "s_register_operand"  "r")
-	  (match_operand:SI 2 "reg_or_int_operand" "rM")]))]
+	 [(match_operand:SI 1 "s_register_operand"  "0,r")
+	  (match_operand:SI 2 "reg_or_int_operand" "l,rM")]))]
   "TARGET_32BIT"
   "* return arm_output_shift(operands, 0);"
   [(set_attr "predicable" "yes")
+   (set_attr "arch" "t2,*")
+   (set_attr "predicable_short_it" "yes,no")
+   (set_attr "length" "2,4")

The first alternative will only be 2 bytes long when predicated or changed into the flag-clobbering form. It should be left as 4 here.

 (define_insn_and_split "*arm_cmpdi_unsigned"
   [(set (reg:CC_CZ CC_REGNUM)
-	(compare:CC_CZ (match_operand:DI 0 "s_register_operand" "r")
-		       (match_operand:DI 1 "arm_di_operand"	"rDi")))]
+	(compare:CC_CZ (match_operand:DI 0 "s_register_operand" "l,r,r")
+		       (match_operand:DI 1 "arm_di_operand"	"Py,r,rDi")))]


'r' constraint for operand 1 on third alternative is now redundant.

OK with the above issues fixed.

R.


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