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Re: [PATCH][ARM][9/n] Partial IT block deprecation in ARMv8 AArch32 - bitwise ops

On 20/06/13 14:50, Kyrylo Tkachov wrote:
Hi all,

This patch adjusts the andsi3, iorsi3, xorsi3 patterns for -mrestrict-it. It
is done by adding 16-bit alternatives that are fit be cond_exec'd when
arm_restrict_it is on.

Tested arm-none-eabi on model and qemu with ARMv7 and ARMv8. Also tested as
part of the series with bootstrap on a Cortex-A15.

Ok for trunk?


2013-06-20  Kyrylo Tkachov  <>

	* config/arm/ (arm_andsi3_insn): Add alternatives for 16-bit
	(iorsi3_insn): Likewise.
	(arm_xorsi3): Likewise.

 ; ??? Check split length for Thumb-2
 (define_insn_and_split "*arm_andsi3_insn"
-  [(set (match_operand:SI         0 "s_register_operand" "=r,r,r,r")
-	(and:SI (match_operand:SI 1 "s_register_operand" "r,r,r,r")
-		(match_operand:SI 2 "reg_or_int_operand" "I,K,r,?n")))]
+  [(set (match_operand:SI         0 "s_register_operand" "=r,l,l,r,r,r")
+	(and:SI (match_operand:SI 1 "s_register_operand" "r,0,l,r,r,r")
+		(match_operand:SI 2 "reg_or_int_operand" "I,l,0,K,r,?n")))]

This operanation is commutative. Rather than adding 0,l and l,0 alternatives, you should mark the entire operation as commutative (with '%' before the first constraint letter for operand 1) and omit the second new alternative.

 (define_insn_and_split "*iorsi3_insn"
-  [(set (match_operand:SI 0 "s_register_operand" "=r,r,r,r")
-	(ior:SI (match_operand:SI 1 "s_register_operand" "%r,r,r,r")
-		(match_operand:SI 2 "reg_or_int_operand" "I,K,r,?n")))]
+  [(set (match_operand:SI 0 "s_register_operand" "=r,l,l,r,r,r")
+	(ior:SI (match_operand:SI 1 "s_register_operand" "%r,0,l,r,r,r")
+		(match_operand:SI 2 "reg_or_int_operand" "I,l,0,K,r,?n")))]

This one is already marked commutative, so the second new alternative should be redundant.

 (define_insn_and_split "*arm_xorsi3"
-  [(set (match_operand:SI         0 "s_register_operand" "=r,r,r")
-	(xor:SI (match_operand:SI 1 "s_register_operand" "%r,r,r")
-		(match_operand:SI 2 "reg_or_int_operand" "I,r,?n")))]
+  [(set (match_operand:SI         0 "s_register_operand" "=r,l,l,r,r")
+	(xor:SI (match_operand:SI 1 "s_register_operand" "%r,0,l,r,r")
+		(match_operand:SI 2 "reg_or_int_operand" "I,l,0,r,?n")))]

Same here.

OK with that change.


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