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Re: [PATCH] Basic support for MIPS r5900

From: "JÃrgen Urban" <JuergenUrban at gmx dot de>
To: "Ian Lance Taylor" <ian at airs dot com>, "Richard Sandiford" <rdsandiford at googlemail dot com>
Cc: gcc-patches at gcc dot gnu dot org
Date: Fri, 14 Jun 2013 20:48:05 +0200 (CEST)
Subject: Re: [PATCH] Basic support for MIPS r5900
References: <trinity-19396fd5-d26f-429c-89a4-e9afbeb36722-1370202342791 at 3capp-gmx-bs38> <87zjv77ygt dot fsf at talisman dot default> <trinity-d20eff1d-14b2-4351-82e3-0e186c9ca625-1370993071149 at 3capp-gmx-bs35> <87k3lz5ecn dot fsf at talisman dot default>, <m3vc5hs4kc dot fsf at pepe dot airs dot com>
Sensitivity: Normal

Hello Richard,

I updated the patch as requested.

> Richard Sandiford <rdsandiford@googlemail.com> writes:
>
> > I can't approve the Makefile.in bits.  I've cc'ed Ian, who's the libgcc
> > maintainer.  Ian: the problem is that "_muldi3.o" on 64-bit targets
> > is actually an implementation of __multi3.  JÃrgen wants to have a
> > __muldi3 too, with the same implementation as on 32-bit targets.
>
> My assumption is that target maintainers can approve target-specific
> changes to libgcc, including Makefile changes.
>
> That said, it seems that this particular patch ought to mostly be in
> libgcc/config/mips/t-mips, using LIB2FUNCS_EXCLUDE and LIB2ADD.  It's
> not clear to me that libgcc/Makefile.in needs any changes, and in case
> it should not be necessary for it to have anything like MIPSTYPE.  That
> kind of thing belongs in config/mips.

The code is now completely moved into libgcc/config/mips/t-mips and libgcc/config/mips/lib2funcs.c (new file).
The code should now be easier to understand.
I used the code from libgcc/config/m32c as example (e.g. same file name lib2funcs.c). I copied the file header (LGPL) from a file which I believed to be new and correct.
You can change it to whatever needed.

Best regards
JÃrgen

Index: gcc/config/mips/mips.h
===================================================================
--- gcc/config/mips/mips.h	(Revision 199708)
+++ gcc/config/mips/mips.h	(Arbeitskopie)
@@ -807,6 +807,7 @@
 #define ISA_HAS_MUL3		((TARGET_MIPS3900                       \
 				  || TARGET_MIPS5400			\
 				  || TARGET_MIPS5500			\
+				  || TARGET_MIPS5900			\
 				  || TARGET_MIPS7000			\
 				  || TARGET_MIPS9000			\
 				  || TARGET_MAD				\
@@ -819,8 +820,25 @@
 /* ISA has a three-operand multiplication instruction.  */
 #define ISA_HAS_DMUL3		(TARGET_64BIT				\
 				 && TARGET_OCTEON			\
+				 && !TARGET_MIPS5900                    \
 				 && !TARGET_MIPS16)
 
+/* ISA supports instructions DMULT and DMULTU. */
+#define ISA_HAS_DMULT           (TARGET_64BIT && !TARGET_MIPS5900)
+
+/* ISA supports instructions MULT and MULTU.
+   This is always supported, but the macro is needed for ISA_HAS_<D>MULT
+   in mips.md.  */
+#define ISA_HAS_MULT		(1)
+
+/* ISA supports instructions DDIV and DDIVU. */
+#define ISA_HAS_DDIV            (TARGET_64BIT && !TARGET_MIPS5900)
+
+/* ISA supports instructions DIV and DIVU.
+   This is always supported, but the macro is needed for ISA_HAS_<D>DIV
+   in mips.md.  */
+#define ISA_HAS_DIV		(1)
+
 #define ISA_HAS_DIV3		((TARGET_LOONGSON_2EF			\
 				  || TARGET_LOONGSON_3A)		\
 				 && !TARGET_MIPS16)
Index: gcc/config/mips/mips.md
===================================================================
--- gcc/config/mips/mips.md	(Revision 199708)
+++ gcc/config/mips/mips.md	(Arbeitskopie)
@@ -1498,9 +1498,11 @@
     }
   else if (TARGET_FIX_R4000)
     emit_insn (gen_mul<mode>3_r4000 (operands[0], operands[1], operands[2]));
-  else
+  else if (ISA_HAS_<D>MULT)
     emit_insn
       (gen_mul<mode>3_internal (operands[0], operands[1], operands[2]));
+  else
+    FAIL;
   DONE;
 })
 
@@ -1527,7 +1529,7 @@
 {
   if (which_alternative == 1)
     return "<d>mult\t%1,%2";
-  if (<MODE>mode == SImode && TARGET_MIPS3900)
+  if (<MODE>mode == SImode && (TARGET_MIPS3900 || TARGET_MIPS5900))
     return "mult\t%0,%1,%2";
   return "<d>mul\t%0,%1,%2";
 }
@@ -1561,7 +1563,7 @@
   [(set (match_operand:GPR 0 "muldiv_target_operand" "=l")
 	(mult:GPR (match_operand:GPR 1 "register_operand" "d")
 		  (match_operand:GPR 2 "register_operand" "d")))]
-  "!TARGET_FIX_R4000"
+  "ISA_HAS_<D>MULT && !TARGET_FIX_R4000"
   "<d>mult\t%1,%2"
   [(set_attr "type" "imul")
    (set_attr "mode" "<MODE>")])
@@ -1571,7 +1573,7 @@
 	(mult:GPR (match_operand:GPR 1 "register_operand" "d")
 		  (match_operand:GPR 2 "register_operand" "d")))
    (clobber (match_scratch:GPR 3 "=l"))]
-  "TARGET_FIX_R4000"
+  "ISA_HAS_<D>MULT && TARGET_FIX_R4000"
   "<d>mult\t%1,%2\;mflo\t%0"
   [(set_attr "type" "imul")
    (set_attr "mode" "<MODE>")
@@ -2038,7 +2040,7 @@
 	(mult:DI (sign_extend:DI (match_operand:SI 1 "register_operand" "d"))
 		 (sign_extend:DI (match_operand:SI 2 "register_operand" "d"))))
    (clobber (match_scratch:DI 3 "=l"))]
-  "TARGET_64BIT && ISA_HAS_DMUL3"
+  "ISA_HAS_DMUL3"
   "dmul\t%0,%1,%2"
   [(set_attr "type" "imul3")
    (set_attr "mode" "DI")])
@@ -2192,7 +2194,7 @@
 	  (mult:TI (any_extend:TI (match_operand:DI 1 "register_operand"))
 		   (any_extend:TI (match_operand:DI 2 "register_operand")))
 	  (const_int 64))))]
-  "TARGET_64BIT && !(<CODE> == ZERO_EXTEND && TARGET_FIX_VR4120)"
+  "ISA_HAS_DMULT && !(<CODE> == ZERO_EXTEND && TARGET_FIX_VR4120)"
 {
   if (TARGET_MIPS16)
     emit_insn (gen_<su>muldi3_highpart_split (operands[0], operands[1],
@@ -2211,7 +2213,7 @@
 		   (any_extend:TI (match_operand:DI 2 "register_operand" "d")))
 	  (const_int 64))))
    (clobber (match_scratch:DI 3 "=l"))]
-  "TARGET_64BIT
+  "ISA_HAS_DMULT
    && !TARGET_MIPS16
    && !(<CODE> == ZERO_EXTEND && TARGET_FIX_VR4120)"
   { return TARGET_FIX_R4000 ? "dmult<u>\t%1,%2\n\tmfhi\t%0" : "#"; }
@@ -2247,7 +2249,7 @@
   [(set (match_operand:TI 0 "register_operand")
 	(mult:TI (any_extend:TI (match_operand:DI 1 "register_operand"))
 		 (any_extend:TI (match_operand:DI 2 "register_operand"))))]
-  "TARGET_64BIT && !(<CODE> == ZERO_EXTEND && TARGET_FIX_VR4120)"
+  "ISA_HAS_DMULT && !(<CODE> == ZERO_EXTEND && TARGET_FIX_VR4120)"
 {
   rtx hilo;
 
@@ -2269,7 +2271,7 @@
   [(set (match_operand:TI 0 "muldiv_target_operand" "=x")
 	(mult:TI (any_extend:TI (match_operand:DI 1 "register_operand" "d"))
 		 (any_extend:TI (match_operand:DI 2 "register_operand" "d"))))]
-  "TARGET_64BIT
+  "ISA_HAS_DMULT
    && !TARGET_FIX_R4000
    && !(<CODE> == ZERO_EXTEND && TARGET_FIX_VR4120)"
   "dmult<u>\t%1,%2"
@@ -2281,7 +2283,7 @@
 	(mult:TI (any_extend:TI (match_operand:DI 1 "register_operand" "d"))
 		 (any_extend:TI (match_operand:DI 2 "register_operand" "d"))))
    (clobber (match_scratch:TI 3 "=x"))]
-  "TARGET_64BIT
+  "ISA_HAS_DMULT
    && TARGET_FIX_R4000
    && !(<CODE> == ZERO_EXTEND && TARGET_FIX_VR4120)"
   "dmult<u>\t%1,%2\;mflo\t%L0\;mfhi\t%M0"
@@ -2577,7 +2579,7 @@
    (set (match_operand:GPR 3 "register_operand" "=d")
 	(mod:GPR (match_dup 1)
 		 (match_dup 2)))]
-  "!TARGET_FIX_VR4120"
+  "ISA_HAS_<D>DIV && !TARGET_FIX_VR4120"
   "#"
   "&& ((TARGET_MIPS16 && cse_not_expected) || reload_completed)"
   [(const_int 0)]
@@ -2599,7 +2601,7 @@
    (set (match_operand:GPR 3 "register_operand" "=d")
 	(umod:GPR (match_dup 1)
 		  (match_dup 2)))]
-  ""
+  "ISA_HAS_<D>DIV"
   "#"
   "(TARGET_MIPS16 && cse_not_expected) || reload_completed"
   [(const_int 0)]
@@ -2644,7 +2646,7 @@
 	  [(any_div:GPR (match_operand:GPR 1 "register_operand" "d")
 			(match_operand:GPR 2 "register_operand" "d"))]
 	  UNSPEC_SET_HILO))]
-  ""
+  "ISA_HAS_<GPR:D>DIV"
   { return mips_output_division ("<GPR:d>div<u>\t%.,%1,%2", operands); }
   [(set_attr "type" "idiv")
    (set_attr "mode" "<GPR:MODE>")])
Index: libgcc/config/mips/t-mips
===================================================================
--- libgcc/config/mips/t-mips	(Revision 199708)
+++ libgcc/config/mips/t-mips	(Arbeitskopie)
@@ -4,3 +4,5 @@
 FPBIT_CFLAGS = -DQUIET_NAN_NEGATED
 DPBIT = true
 DPBIT_CFLAGS = -DQUIET_NAN_NEGATED
+
+LIB2ADD = $(srcdir)/config/mips/lib2funcs.c
--- /dev/null	2013-06-14 11:13:13.590602001 +0200
+++ libgcc/config/mips/lib2funcs.c	2013-06-14 20:32:25.926290077 +0200
@@ -0,0 +1,44 @@
+/* libgcc routines for MIPS
+   Copyright (C) 2013 Free Software Foundation, Inc.
+   DMULT/DDIV replacement support by Juergen Urban, JuergenUrban@gmx.de.
+
+This file is part of GCC.
+
+GCC is free software; you can redistribute it and/or modify it under
+the terms of the GNU General Public License as published by the Free
+Software Foundation; either version 3, or (at your option) any later
+version.
+
+GCC is distributed in the hope that it will be useful, but WITHOUT ANY
+WARRANTY; without even the implied warranty of MERCHANTABILITY or
+FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+for more details.
+
+Under Section 7 of GPL version 3, you are granted additional
+permissions described in the GCC Runtime Library Exception, version
+3.1, as published by the Free Software Foundation.
+
+You should have received a copy of the GNU General Public License and
+a copy of the GCC Runtime Library Exception along with this program;
+see the files COPYING3 and COPYING.RUNTIME respectively.  If not, see
+<http://www.gnu.org/licenses/>.  */
+
+#if defined(__mips64) && defined(_MIPS_ARCH_R5900)
+
+/* Build DI version of libgcc functions. */
+#define LIBGCC2_UNITS_PER_WORD 4
+
+/* The following function is needed when !ISA_HAS_DMULT. */
+#define L_muldi3
+
+/* The following functions are needed when !ISA_HAS_DDIV. */
+#define L_divdi3
+#define L_moddi3
+#define L_udivdi3
+#define L_umoddi3
+#define L_udivmoddi4
+
+/* Use generic definition of functions. */
+#include "libgcc2.c"
+
+#endif

Follow-Ups:
- Re: [PATCH] Basic support for MIPS r5900
  - From: Ian Lance Taylor
- Re: [PATCH] Basic support for MIPS r5900
  - From: Richard Sandiford

References:
- [PATCH] Basic support for MIPS r5900
  - From: "JÃrgen Urban"
- Re: [PATCH] Basic support for MIPS r5900
  - From: Richard Sandiford
- Aw: Re: [PATCH] Basic support for MIPS r5900
  - From: "JÃrgen Urban"
- Re: Aw: Re: [PATCH] Basic support for MIPS r5900
  - From: Richard Sandiford
- Re: Aw: Re: [PATCH] Basic support for MIPS r5900
  - From: Ian Lance Taylor

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