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Re: [PATCH, rs6000] power8 patches, patch #6, direct move & basic quad load/store
- From: David Edelsohn <dje dot gcc at gmail dot com>
- To: Michael Meissner <meissner at linux dot vnet dot ibm dot com>, GCC Patches <gcc-patches at gcc dot gnu dot org>, Pat Haugen <pthaugen at us dot ibm dot com>, Peter Bergner <bergner at vnet dot ibm dot com>
- Date: Mon, 10 Jun 2013 11:41:20 -0400
- Subject: Re: [PATCH, rs6000] power8 patches, patch #6, direct move & basic quad load/store
- References: <20130520204053 dot GA21090 at ibm-tiger dot the-meissners dot org> <20130522142533 dot GA25178 at ibm-tiger dot the-meissners dot org> <CAGWvnymbak8QhR88gcNe-+_CAfAKa_jbFLTYf+g_cUPxk2Y0PQ at mail dot gmail dot com> <20130529203207 dot GA24280 at ibm-tiger dot the-meissners dot org>
Mike,
This patch is okay, but something seems really broken with respect to
TImode. I don't know if we have to separate TImode from V1TImode or
some distinction for atomics from other uses of TImode. This isn't
like float modes where they mostly live in FPRs and only occassionally
need to live in GPRs. TImode between VSX and GPRs really is bimodal.
Something is wrong with this preferencing design.
Maybe we need a separate set of logical TImode instructions for the
atomic ops with a neutral set of preferences on the constraints for
movti. Then the registers chosen for the computation will correctly
drive the register allocation decisions.
Thanks, David